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參數(shù)資料
| 型號： | AD7760BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 2.5MSPS 64TQFP |
| 標準包裝： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 2.5M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 958mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應商設備封裝： | 64-TQFP-EP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
| 產品目錄頁面： | 779 (CN2011-ZH PDF) |
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AD7760
Rev. A | Page 24 of 36
CLOCKING THE AD7760
The AD7760 requires an external low jitter clock source. This
signal is applied to the MCLK pin, and the MCLKGND pin is
used to sense the ground from the clock source. An internal
clock signal (ICLK) is derived from the MCLK input signal. The
ICLK controls all internal operations of the AD7760. The
maximum ICLK frequency is 20 MHz, but due to an internal
clock divider, a range of MCLK frequencies can be used. There
are two ways to generate the ICLK:
ICLK = MCLK (CDIV = 1)
ICLK = MCLK/2 (CDIV = 0)
These options are selected from the control register (see the
AD7760 Registers section for more details). On power-up, the
default is ICLK = MCLK/2 to ensure that the part can handle
the maximum MCLK frequency of 40 MHz. For output data
rates equal to those used in audio systems, a 12.288 MHz ICLK
frequency can be used. As shown in Table 6, output data rates of
192 kHz, 96 kHz, and 48 kHz are achievable with this ICLK
frequency. As mentioned previously, this ICLK frequency can
be derived from different MCLK frequencies.
It is recommended that the MCLK signal applied to the
AD7760 has a 50-50 mark-space ratio. When operating in clock
divide-by-1 mode (that is, CDIV = 1), using higher mark-space
ratios reduces the maximum MCLK frequency that can be
applied to the AD7760 yielding maximum performance. For
example, using a mark-space ratio of 60-40 (with CDIV = 1)
reduces the maximum MCLK frequency that will yield the
maximum INL and THD performance to 16 MHz.
BUFFERING THE MCLK SIGNAL
The MCLK signal for the AD7760 must be buffered before
being input to the MCLK pin on the AD7760 device. This can
be done simply by routing the MCLK signal to both inputs of an
AND gate (see Figure 47).
The recommended buffer is the NC7SZ08M5, which is a two-
input AND gate from Fairchild Semiconductor. Using the buffer
with a supply voltage of 5 V is advised to achieve optimum
performance from the AD7760.
3
MCLK
SOURCE
NC7SZ08M5
(AND GATE)
AD7760
0
497
5-
054
Figure 47. Buffering the MCLK Signal Using the NC7SZ08M5 AND Gate
MCLK JITTER REQUIREMENTS
The MCLK jitter requirements depend on a number of factors
and are given by
20
)
(
10
2
)
(
dB
SNR
f
OSR
t
IN
rms
j
×
π
×
=
where:
OSR = oversampling ratio = fICLK/ODR.
fIN = maximum input frequency.
SNR(dB) = target SNR.
Example 1
This example can be taken from Table 6, where:
ODR = 2.5 MHz.
fICLK = 20 MHz.
fIN (max) = 1 MHz.
SNR = 108 dB.
ps
79
.
1
10
2
8
4
.
5
6
)
(
=
×
π
×
=
rms
j
t
This is the maximum allowable clock jitter for a full-scale,
1 MHz input tone with the given ICLK and output data rate.
Example 2
Take a second example from Table 6, where:
ODR = 48 kHz.
fICLK = 12.288 MHz.
fIN (max) = 19.2 kHz.
SNR = 120 dB.
ps
133
10
2
.
19
2
256
6
3
)
(
=
×
π
×
=
rms
j
t
The input amplitude also has an effect on these jitter figures.
For example, if the input level was 3 dB below full-scale, the
allowable jitter would be increased by a factor of √2, increasing
the first example to 2.53 ps rms. This happens when the
maximum slew rate is decreased by a reduction in amplitude.
maximum slew rate of a sine wave of the same frequency but
with different amplitudes.
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| AD7760BSVZ-REEL | 功能描述:IC ADC 24BIT 2.5MSPS 64TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7761BSTZ | 功能描述:16 Bit Analog to Digital Converter 8 Input 8 Sigma-Delta 64-LQFP (10x10) 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):有效 位數(shù):16 采樣率（每秒）:256k 輸入數(shù):8 輸入類型:差分 數(shù)據(jù)接口:SPI 配置:ADC 無線電 - S/H:ADC:- A/D 轉換器數(shù):8 架構:三角積分 參考類型:外部 電壓 - 電源，模擬:2 V ~ 5.5 V 電壓 - 電源，數(shù)字:- 特性:同步采樣 工作溫度:-40°C ~ 105°C 封裝/外殼:64-LQFP 供應商器件封裝:64-LQFP（10x10） 標準包裝:1 |
| AD7761BSTZ-RL | 功能描述:16 Bit Analog to Digital Converter 8 Input 8 Sigma-Delta 64-LQFP (10x10) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 位數(shù):16 采樣率（每秒）:256k 輸入數(shù):8 輸入類型:差分 數(shù)據(jù)接口:SPI 配置:ADC 無線電 - S/H:ADC:- A/D 轉換器數(shù):8 架構:三角積分 參考類型:外部 電壓 - 電源，模擬:2 V ~ 5.5 V 電壓 - 電源，數(shù)字:- 特性:同步采樣 工作溫度:-40°C ~ 105°C 封裝/外殼:64-LQFP 供應商器件封裝:64-LQFP（10x10） 標準包裝:1,500 |
| AD7762 | 制造商:AD 制造商全稱:Analog Devices 功能描述:24-Bit, 8.5 mW, 109 dB, 128/64/32 kSPS ADCs |
| AD77628SVZ | 制造商:Analog Devices 功能描述: |
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