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| 型號： | AD7760BSVZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 2.5MSPS 64TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 2.5M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 958mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP-EP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
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AD7760
Rev. A | Page 34 of 36
STATUS REGISTER (READ ONLY)
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PART 1
PART 0
DIE 2
DIE 1
DIE 0
0
LPWR
OVR
DL_OK
FILTOK
UFILT
BYP F3
BYP F1
DEC2
DEC1
DEC0
Table 17. Bit Descriptions of Status Register
Bit
Mnemonic
Comment
15, 14
PART [1:0]
Part Number. These bits are constant for the AD7760.
13 to 11
DIE [2:0]
Die Number. These bits reflect the current AD7760 die number for identification purposes within a system.
10
0
This bit is set to 0.
9
LPWR
Low Power. If the AD7760 is operating in low power mode, this bit is set to 1.
8
OVR
If the current analog input exceeds the current overrange threshold, this bit is set.
7
DL_OK
When downloading a user filter to the AD7760, a checksum is generated. This checksum is compared to the one
downloaded following the coefficients. If these checksums agree, this bit is set.
6
FILTOK
When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter. This
generated checksum is compared to the one downloaded. If they match, this bit is set.
5
UFILT
If a user-defined filter is in use, this bit is set.
4
BYP F3
Bypass Filter 3. If Filter 3 is bypassed by setting the relevant bit in Control Register 1, this bit is also set.
3
BYP F1
Bypass Filter 1. If Filter 1 is bypassed by setting the relevant bit in Control Register 1, this bit is also set.
2 to 0
DEC [2:0]
Decimation Rate. These bits correspond to the bits set in Control Register 1.
OFFSET REGISTER—ADDRESS 0x0003
Non-bit-mapped, Default Value 0x0000
The offset register uses twos complement notation and is scaled
such that 0x7FFF (maximum positive value) and 0x8000 (max-
imum negative value) correspond to an offset of +0.78125% and
0.78125%, respectively. Offset correction is applied after any
gain correction. Using the default gain value of 1.25 and assuming
a reference voltage of 4.096 V, the offset correction range is
approximately ±25 mV.
GAIN REGISTER—ADDRESS 0x0004
Non-bit-mapped, Default Value 0xA000
The gain register is scaled such that 0x8000 corresponds to a
gain of 1.0. The default value of this register is 1.25 (0xA000).
This results in a full-scale digital output when the input is at
80% of VREF, tying in with the maximum analog input range of
±80% of VREF p-p.
OVERRANGE REGISTER—ADDRESS 0x0005
Non-bit-mapped, Default Value 0xCCCC
The overrange register value is compared with the output of
the first decimation filter to obtain an overload indication with
minimum propagation delay. This is prior to any gain scaling
or offset adjustment. The default value is 0xCCCC, which
corresponds to 80% of VREF (the maximum permitted analog
input voltage). Assuming VREF = 4.096 V, the bit is then set when
the input voltage exceeds approximately 6.55 V p-p differential.
Once the overrange bit is set, the DVALID bit in the status bits
of the AD7760 ouptut is set to zero, providing another indication
that an input overrange has occurred. Note that the overrange
bit is set immediately if the analog input voltage exceeds 100% of
VREF for more than four consecutive samples at the modulator rate.
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