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參數(shù)資料
| 型號： | AD775 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 8-Bit 20 MSPS, 60 mW Sampling A/D Converter(8位,20MSPS 60mW采樣A/D轉(zhuǎn)換器) |
| 中文描述： | 8位20 MSPS的60毫瓦采樣A / D轉(zhuǎn)換器（8位，20MSPS 60mW的采樣的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 343K |
| 代理商： | AD775 |
AD775
REV. 0
–9–
POWE R SUPPLY CONNE CT IONS AND DE COUPLING
T he analog and digital supplies of the AD775 have been sepa-
rate to prevent the typically large transients associated with the
on-chip digital circuitry from coupling into the analog supplies
(AV
DD
, AV
SS
). However, in order to avoid possible latch-up
conditions, AV
DD
and DV
DD
must share a common supply
external to the part, preferably a common source somewhere on
the PC board.
Each supply should be decoupled by a 0.1
μ
F capacitor located
as close to the device pin as possible. Surface-mount capacitors,
by virtue of their low parasitic inductance, are preferable to
through-hole types. A larger capacitor (10
μ
F electrolytic)
should be located somewhere on the board to help decouple
large, low frequency supply noise. For specific layout informa-
tion, refer to the AD775 Evaluation Board section of the data
sheet.
J6
C15
D
C13
A
J3
TP4
V
RT
C12
+5V
D
C18
+5VA
J9
J5
C14
J4
TP3
VRB
3
2
1
AD822
C4
390pF
R10
20
1/2 U2
R9
10k
8
C9
A
+5VA
6
AD822
7
C3
390pF
R5
20
1/2 U2
R6
10k
J2
5
4
A
A
R7
10k
A
A
9
3
4
5
1
2
6
7
8
10
G1
A1
A2
A3
A4
A5
A6
A7
A8
GND
74ALS541
12
18
17
16
20
19
15
14
13
11
D
D
C22
+5V
V
CC
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
TP13
ENABLE
J10
D
D
D
1
40
D
P2-40 PIN IDC
A
R8
10k
D
3
2
U1
V
IN
V
OUT
GND
AD680
1
A
+5VA
A
C2
R3
499
C1
A
R2
500
R1
500
R11
75
R12
4.99k
3
2
6
AD817
U3
7
C6
A
C8
22
μ
F
R13
20
Q1
2N3904
TP2
R4
49.9
A
TP1
J1
ANALOG
INPUT
4
C5
V
EE
V
CC
V
EE
A
V
CC
R14
500
+5VA
R15
499
CR1
1N4148
+5VA
A
C7
10pF
TP5
V
IN
TP10
R16
49.9
D
TP9
J8
CLOCK
( )
5
6
1/6
U7
9
8
1/6
U7
13
14
17
18
19
15
16
20
21
22
23
24
2
12
11
8
7
6
10
9
5
4
3
1
DV
SS
D2
D3
D4
D0
D1
D5
D6
D7
DV
DD
CLK
OE
V
RB
AV
SS
V
IN
AV
DD
AV
SS
V
RT
V
RTS
AV
DD
AV
DD
DV
DD
DV
SS
V
RBS
AD775
= 47
F ELECTROLYTIC CAPACITOR
UNLESS OTHERWISE NOTED
= 0.1
F CERAMIC CAPACITOR
UNLESS OTHERWISE NOTED
NOTES
V
IN
V
OUT
GND
U4
78M05
J7
C11
D
C21
TP12
TP6
+5V
+5VA
A
V
CC
C16
C20
C19
TP7
TP8
TP11
V
CC
V
EE
1
2
3
4
5
6
V
EE
U5
U6
Figure 17. AD775 Evaluation Board Schematic
APPLICAT IONS
AD775 E VALUAT ION BOARD
Figures 17 through 22 show the schematic and printed circuit
board (PCB) layout for the AD775 evaluation board. Referring
to Figure 17, the input signal is buffered by U3, an AD817 op
amp configured as a unity-gain follower. T he signal is then ac-
coupled and dc-biased by adjusting potentiometer R14. Video
and imaging applications would typically use a dc-restoration
circuit instead of the manual potentiometer adjustment. Q1, an
emitter-follower, buffers the input signal and provides ample
current to drive a simple low-pass filter. T he filtering is included
to limit wideband noise and highlight the fact that the AD775
can be driven from a nonzero source impedance.
T he reference circuit is similar to the one shown in Figure 11
with the exception that R1 and R2 allow precise adjustment of
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