
AD775
REV. 0
–7–
In the topology shown in Figure 8, the top of the ladder (V
RT
)
is shorted to the top bias resistor (V
RT S
) (Pin 17 shorted to Pin
16), while the bottom of the ladder (V
RB
) is shorted to the bot-
tom bias resistor (V
RBS
) (Pin 23 shorted to Pin 22). T his creates
a resistive path (nominally 725 ohms) between AV
DD
and AV
SS
.
For nominal supply voltages (5 V and 0 V respectively), this
creates an input range of 0.64 V to 2.73 V.
Both top and bottom of the reference ladder should be de-
coupled, preferably with a chip capacitor to ground to minimize
reference noise.
T he topology shown in Figure 9 provides a ground-inclusive
input range. T he bottom of the ladder (V
RB
) is shorted to AV
SS
.
(0 V), while the top of the ladder (V
RT
) is connected to the on-
board bias resistor (V
RT S
). T his provides a nominal input range
of 0 V to +2.4 V for AV
DD
of 5 V. T he V
RBS
pin may be left
floating, or shorted to AV
SS
.
16
23
17
22
AV
DD
325
AV
SS
90
300
AD775
*VALUES FOR
RESISTANCE
ARE TYPICAL
0.1
μ
F
AV
SS
Figure 9. Reference Configuration: 0 V to +2.4 V
More elaborate topologies can be used for those wishing to
provide an input span based on an external reference voltage.
T he circuit in Figure 10 uses the AD780 2.5 V reference to
drive the top of the ladder (V
RT
), with the bottom (V
RB
) of the
ladder grounded to provide an input span of 0 V to +2.5 V. T his is
modified in Figure 11 to shift the 2.5 V span up 700 mV.
16
22
17
23
AD775
NC
NC
NC = NO CONNECT
0.1
μ
F
AD780
5
6
7
8
NC
NC
NC
1
NC
4
3
2
NC
0.1
μ
F
+5V
Figure 10. Reference Configuration: 0 V to 2.5 V
T he AD775 can accommodate dynamic changes in the reference
voltage for gain or offset adjustment. However, conversions that
are in progress, including those in the converter pipeline, while
the reference voltages are changing will be invalid.
16
22
17
23
AD775
NC
NC
NC = NO CONNECT
0.1
μ
F
V
RTS
V
RT
V
RBS
V
RB
1
3
2
AD822
500pF
10k
20
10k
0.1
μ
F
7
5
6
AD822
500pF
10k
20
10k
0.1
μ
F
422
140
422
1
3
2
V
OUT
GND
V
IN
AD680
0.1
μ
F
+5V
Figure 11. Reference Configuration: 0.7 V to 3.2 V
ANALOG INPUT
T he impedance looking into the analog input is essentially
capacitive, as shown in the equivalent circuit of Figure 12, typi-
cally totalling around 11 pF. A portion of this capacitance is
parasitic; the remainder is part of the switched capacitor struc-
ture of the comparator arrays. T he switches close on the rising
edge of the clock, acquire the input voltage, and open on the
clock’s falling edge (the sampling instant). T he charge that must
be moved onto the capacitors during acquisition will be a func-
tion of the converter’s previous two samples, but there should be
no sample-to-sample crosstalk so long as ample driving imped-
ance and acquisition time are provided.
SWITCHES EACH
CLOCK CYCLE
C2
SWITCHES ON ALTERNATE
CLOCK CYCLES
C3
C1
AV
SS
AV
DD
C1 + C2 + C3
≈
11pF
V
IN
AD775
Figure 12. Equivalent Analog Input Circuit (V
IN
)
For example, to ensure accurate acquisition (to 1/4 bit accuracy)
of a full-scale input step in less than 20 ns, a source impedance
of less than 100 ohms is recommended. Figure 13 shows one
option of input buffer circuitry using the AD817. T he AD817
acts as both an inverting buffer and level shifting circuit. In
order to level shift the ground-based input signal to the dc level
required by the input of the AD775, the supply voltage is resis-
tively divided to produce the appropriate voltage at the nonin-
verting input of the AD817. For most applications, the AD817
provides a low cost, high performance level shifter. T he AD811
is recommended for systems which require faster settling times.