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參數(shù)資料
| 型號(hào)： | AD7716BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 22BIT SIGMA-DELTA 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 22 |
| 采樣率（每秒）： | 2.23k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個(gè)單端，雙極 |
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REV. A
AD7716
–12–
Control register bit, DB15 (A3), acts as an extra address bit
which must always be set to 1 to enable programming of the
AD7716. If it is set to 0, then the programmed word is ignored.
This allows the user to bypass the AD7716 control register and
use the serial stream from the DSP or microcomputer to pro-
gram other serial peripheral devices.
When a valid word has been received, the device interrogates
the M0 bit. If this is 0, then the digital filter cutoff frequencies
are programmed to the appropriate value if the device address
pins correspond to the A2, A1, A0 bits in the control register. If
the device address pins do not correspond to the A2, A1, A0
bits then the FC2, FC1, FC0 bits are ignored. If M0 is 1, then
the digital filter cutoff frequencies are programmed to the FC2,
FC1, FC0 value irrespective of the address bits. In a multi-
channel system this allows the user to either program all
AD7716s to have the same cutoff frequency or else to give each
device a separate cutoff frequency.
Control register bits FC2, FC1, FC0 program the digital filter
cutoff frequency, see Table VI.
Control register bits D2, D1 control the digital output pins D2
and D1. These are programmed in the same way as FC2, FC1,
FC0.
CONTROL REGISTER DESCRIPTION
The 16-bit control register is programmed in two 8-bit bytes;
the low byte is programmed first and the high byte second. The
loading format is LSB first (DB0 for the Least Significant Byte;
DB8 for the Most Significant Byte). Three control lines are
used: TFS, SCLK and SDATA. On initial application of
power to the AD7716, the control register will come up in an
undetermined state. Programming the control register requires
an SCLK input, a TFS input and an SDATA input. The
MODE pin on the device determines whether it is in the master
interface mode or the slave interface mode. In either mode, a
falling edge on TFS causes the part to relinquish control of the
SDATA and SCLK lines. When TFS goes low, data on the
SDATA line is clocked into the control register on each suc-
ceeding falling edge of SCLK. When 8 bits have been clocked
in, the transfer automatically stops. Only when another negative
going edge is detected on TFS will new information be written
into the control register. The control register programming
model is shown in Table II. Bits DB8 and DB0 allow the con-
trol register to identify whether the MS Byte or the LS Byte has
been programmed. Only when DB8 is a 1 and DB0 is a 0 will
the register recognize that a complete valid word has been
programmed.
Table II. Control Register Programming Model
Most Significant Byte
Least Significant Byte
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
A3
A2
A1
A0
M0
FC2
FC1
1
FC0
DOUT2 DOUT1
X
0
Table III. M0 Truth Table
M0
Programming Mode
0
A2, A1, A0 determine which device is addressed and
programmed with cutoff frequency and digital output.
1
A2, A1, A0 ignored. All devices are addressed and
programmed with common cutoff frequency and digital
output.
Table IV. Cutoff Frequency Truth Table
FC2
FC1
FC0
Cutoff Frequency (Hz)
000
584
001
292
010
146
011
73
1
0
36.6
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