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參數(shù)資料
| 型號(hào)： | AD7716BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 22BIT SIGMA-DELTA 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 22 |
| 采樣率（每秒）： | 2.23k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個(gè)單端，雙極 |
REV. A
–7–
AD7716
PIN DESCRIPTION
Pin
Description
AVDD
Analog Positive Supply, +5 V Nominal. This supplies +ve power to the analog modulators. AVDD & DVDD
must be tied together externally.
DVDD
Digital Positive Supply, +5 V Nominal. This supplies +ve power to the digital filter and input/output registers.
AVSS
Analog Negative Supply, –5 V nominal. This supplies –ve power to the analog modulators.
RESET
A high pulse on this input pin synchronizes the sampling point on the four input channels. It can be used in a
multichannel system to ensure simultaneous sampling. This also resets the digital interface to a known state.
A0–A2
The three address input pins, A0, A1 and A2 give the device a unique address. This information is contained in
the output data stream from the device.
CLKIN
Clock Input for External Clock.
CLKOUT
Clock Output which is used to generate an internal master clock by connecting a crystal between CLKOUT and
CLKIN. If an external clock is used then CLKOUT is not connected.
MODE
This digital input determines the device interface mode. If it is hardwired low, then the Master Mode interface is
enabled whereas if it is high, the Slave Mode interface is enabled.
CASCIN
This is an active-high, level-triggered digital input which is used to enable the output data stream. This input
may be used to cascade several devices in a multichannel system.
CASCOUT
Digital output which goes high at the end of a complete 4-channel data transfer. This can be connected to the
CASCIN of the next device in a multichannel system to ensure proper control of the data transfer.
RFS
Receive Frame Synchronization signal for the serial output data stream. This can be an input or output depending
on the interface mode.
SDATA
Serial Data Input/Output Pin.
SCLK
Serial Clock Input/Output. The SCLK pin is configured as an input or output, depending on the state of the
Mode pin.
DRDY
Data Ready Output. A falling edge indicates that a new word is available for transmission. It will return high
when 4, 32-bit words have been transmitted. It also goes high for one clock cycle, when a new word is being
loaded into the output register. Data should not be read during this period.
TFS
Transmit Frame Sync input for programming the on-chip Control Register.
DIN1
Digital Data Input. This is contained in the digital data stream sent from the device.
DOUT1, DOUT2
Digital Outputs. These two digital outputs can be programmed from the on-chip Control Register. They can
be used to control calibration signals at the front end.
VREF
Reference Input, Nominally 2.5 V.
AGND
Analog Ground. Ground reference for analog circuitry.
DGND
Digital Ground. Ground return for digital circuitry.
AIN1–AIN4
Analog Input Pins. The analog input range is
±2.5 V.
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