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參數(shù)資料
| 型號(hào)： | AD7716BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 22BIT SIGMA-DELTA 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 22 |
| 采樣率（每秒）： | 2.23k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個(gè)單端，雙極 |
REV. A
AD7716
–4–
Limit at TMIN, TMAX
Parameter
(B Version)
Units
Conditions/Comments
fCLKIN
3, 4
400
kHz min
CLKIN Frequency
8
MHz max
tr
5
40
ns max
Digital Output Rise Time. Typically 20 ns
tf
5
40
ns max
Digital Output Fall Time. Typically 20 ns
t7
1/fCLKIN
ns min
CASCIN Pulse Width
t8
1/fCLKIN
ns min
CASCIN to DRDY Setup Time
t9
1/2fCLKIN + 30
ns max
DRDY
Low to SCLK Low Delay
t10
50
ns max
CLKIN High to DRDY Low, SCLK Active, RFS Active
t11
40
ns max
CLKIN High to SCLK High Delay
t12
50
ns min
SCLK Width
t13
1/fCLKIN
ns
SCLK Period
t14
40
ns max
SCLK High to RFS High Delay
t15
1/fCLKIN
ns
RFS
Pulse Width
t16
6
45
ns max
SCLK High to SDATA Valid Delay
t17
7
1/2fCLKIN + 50
ns max
SCLK Low to SDATA High Impedance Delay
1/2fCLKIN + 10
ns min
t18
1/2fCLKIN + 60
ns max
CLKIN High to DRDY High Delay
t19
50
ns max
CLKIN High to RFS High Impedance, SCLK High Impedance
20
ns min
t20
1/2fCLKIN + 50
ns max
SCLK Low to CASCOUT High Delay
t21
2/fCLKIN
ns
CASCOUT Pulse Width
NOTES
1Sample tested at +25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 1 and 3.
3CLKIN duty cycle range is 40% to 60%.
4The AD7716 is production tested with f
CLKIN at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz and 8 MHz in master mode.
5Specified using 10% and 90% points on waveform of interest.
6t
16 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
7t
17 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
MASTER MODE TIMING CHARACTERISTICS1, 2 (AV
DD = DVDD = +5 V
5%; AVSS = –5 V
5%; AGND = DGND = 0 V;
fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)
Figure 3. Master Mode Timing Diagram
DB31
CH1
t
20
t
21
CASCIN (I)
SCLK (O)
RFS (O)
SDATA (O)
CASCOUT (O)
t
17
t
8
t
7
t
18
t
19
t
9
t
11
t
10
t
12
t
13
t
12
t
19
t
15
t
14
t
16
DB30
CH1
DB29
CH1
DB25
CH1
DB24
CH1
DB23
CH1
DB2
CH4
DB1
CH4
DB0
CH4
CLKIN (I)
DRDY (O)
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