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| 型號： | AD7716BPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 22BIT SIGMA-DELTA 44-PLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 22 |
| 采樣率（每秒）： | 2.23k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個單端，雙極 |
| 產(chǎn)品目錄頁面： | 778 (CN2011-ZH PDF) |
REV. A
–9–
AD7716
GENERAL DESCRIPTION
The AD7716 is a 4-channel 22-bit A/D converter with on-chip
digital filtering, intended for the measurement of wide dynamic
range, low frequency signals such as those representing ECG,
EEG, chemical, physical or biological processes. It contains
four sigma delta ADCs, a clock oscillator and a serial communi-
cations port.
Each of the analog input signals to the AD7716 is continuously
sampled at a rate determined by the frequency of the master
clock, CLKIN. Four sigma-delta modulators convert the
sampled signals into digital pulse trains whose duty cycles con-
tain the digital information. These are followed by low-pass fil-
ters to process the output of the modulators and update the
output register at a maximum rate of 2.2 kHz. The output data
can be read from the serial port at any rate up to this.
THEORY OF OPERATION
The general block diagram of a delta-sigma ADC is shown in
Figure 5. It contains the following elements:
1. Continuously Sampling Integrator
2. A Differential Amplifier or Subtracter
3. A 1-Bit A/D Converter (Comparator)
4. A 1-Bit DAC
5. A Digital Low-Pass Filter
In operation, the sampled analog signal is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, whose output samples the differ-
ence signal at a frequency many times that of the analog signal
frequency (oversampling).
Oversampling is fundamental to the operation of delta-sigma
ADCs. Using the quantization noise formula for an ADC:
SNR = (6.02
number of bits + 1.76) dB,
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
When operating with a master clock of 8 MHz, the AD7716
samples the input signal at 570 kHz, which spreads the quanti-
zation noise from 0 kHz to 285 kHz. Since the specified analog
input bandwidth of the AD7716 is only 584 Hz maximum (it
can be programmed to be lower), the noise energy in this band-
width would be only 1/488 of the total quantization noise, as-
suming that the noise energy was spread evenly throughout the
spectrum. This very high sampling with respect to the input
bandwidth is known as oversampling, and the ratio of 488:1 is
called the oversampling ratio. The noise is reduced still further
by analog filtering in the modulator loop, which shapes the
quantization noise spectrum to move most of the noise energy to
frequencies above 584 Hz. The SNR performance in the 0 Hz
to 584 Hz range is conditioned to the 99 dB level in this fashion
(see Table I). As the programmed bandwidth is reduced, the
oversampling ratio increases and the usable dynamic range also
increases. Thus, for example, with a programmed bandwidth
of 73 Hz, the oversampling ratio is 3904:1, and the usable dy-
namic range is 108 dB which corresponds to greater than 17-bit
resolution.
The output of the comparator provides the digital input for the
1-bit DAC, so the system functions as a negative feedback loop
which minimizes the difference signal. The digital data that rep-
resents the analog input voltage is in the duty cycle of the pulse
train appearing at the output of the comparator. It can be re-
trieved as a parallel binary data word using a digital filter.
+V
REF
–V
REF
INTEGRATOR
STROBED
COMPARATOR
CLOCK
C
TO
DIGITAL
FILTER
R
A
IN
1-BIT DAC
EN
Figure 5. First Order Modulator
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first order sigma-
delta ADC is shown in Figure 5. This contains only a first-
order low-pass filter or integrator.
The AD7716 uses a second-order sigma-delta modulator and a
digital filter that provides a rolling average of the sampled out-
put. After power-up or if there is a step change in the input
voltage, there is a settling time before valid data is obtained.
DIGITAL FILTERING
The AD7716’s digital filter behaves like an analog filter, with a
few minor differences.
First, since digital filtering occurs after the A-to-D conversion
process, it can remove noise injected during the conversion pro-
cess. Analog filtering cannot do this.
On the other hand, analog filtering can remove noise super-
imposed on the analog signal before it reaches the ADC. Digital
filtering cannot do this and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. If noise signals cause the input signal to exceed
the specified range, consideration should be given to analog in-
put filtering, or to reducing the gain in the input channel to
bring the combination of signal and noise spike within the speci-
fied input range.
Filter Characteristics
The cutoff frequency of the digital filter is determined by bits
FC2, FC1 and FC0 in the control register (See Table IV). The
cutoff frequency of the filter is fCLKIN /(3.81
14
256
2N),
where N is the decimal equivalent of FC2, FC1, FC0. At the
maximum clock frequency of 8 MHz, with all 0s loaded to FC2,
FC1, FC0, the cutoff frequency of the filter is 584 Hz and the
data update rate is 2232 Hz.
Since the AD7716 contains low-pass filtering, there is a settling
time associated with step function inputs, and data will be in-
valid after a step change until the settling time has elapsed. The
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