
==99-10-14==
P&S
ooá|′μ×ó1é· YóDT1
==46-11==
P &S
oo á|′μ×ó1é· YóDT1
μ :
ot±±ooêD×μèa· 15o
D :
ooêD70020D
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430079
μ°:
( 86) ( 027£87493500 87493506
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( 86) ( 027) 87491166, 87493497
P &S
í í :
http://www.p8s.com
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17.
óú
f
CLKIN
=2.4576MHz
μê μò¨ Y
8
£2¨÷ ′÷μ
BST
±Da
1
£óú
é£üéò±a
0
£
18.
μ±ó
MCLK
òyê1ó§ìòì′éD3÷×÷a÷tμê±ó′ê±£
DV
DD
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òD3÷μààDí±ˉ£¨ °ê±óoíμ′÷μ· ±òú££
19.
ú±á÷2aá2¢óóúù μí¨′ £ó
5Hz
¢
10Hz
¢
25Hz
ò
50Hz
μ2¨÷°ú£
50Hz
μ
PSRR
31y
120dB
£ó
6Hz
¢
10Hz
¢
30Hz
ò
60Hz
μ2¨÷°ú£
60Hz
μ
PSRR
31y
120dB
£
20. PSSR
è óúò £óúòa
1
£μDíμa
70dB
£óúòa
2
£μDíμa
75dB
£óúòa
4
£μDíμa
80dB
£óúòa
8
á
128
£μDíμa
85dB
£
21.
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5V
μ′ê±′yúμá÷μμDíμóμ
150
|ì
A
£
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3.3V
μ′ê±óμ
75
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A
£μ±ú
MCLK
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òú££ê1 éü2ó¨ ± £
2. 2. 4 AD7714YμìD
£¨
AV
DD
=DV
DD
=+2.7V
á
+3.3V
ò
4.75V
á
5.25V
£
REFIN
£¨
+
£
=+1.25V
£¨ú
AV
DD
=3V
é£í
+2.5V
£¨ú
AV
DD
=5V
é£
REFIN
£¨£-£
=AGND
£3y· áí óDμ÷
MCLK IN= 2.4576MHz
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T
MIN
á
T
MAX
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Parameter
Y Versions
Units
LOGIC OUTPUTS (Continued)
V
, Output High Voltage
DV
DD
0.6
V min
Floating State Leakage Current
10
A max
Floating State Output Capacitance
13
9
pF typ
Data Output Coding
Binary
Offset Binary
TRANSDUCER BURNOUT
14
Current
1
A nom
Initial Tolerance
10
% typ
Drift
0.1
%/ C typ
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
15
(1.05 V
REF
)/GAIN
V max
Negative Full-Scale Calibration Limit
15
(1.05 V
REF
)/GAIN V max
Offset Calibration Limit
16
(1.05 V
REF
)/GAIN V max
Input Span
0.8 V
REF
V min
(2.1 V
REF
)/GAIN
V max
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
Voltage
+2.7 to +3.3 or
V
+4.75 to +5.25
V
DV
Voltage
+2.7 to +5.25
V
Power Supply Currents
AV
DD
Current
0.28
mA max
0.6
mA max
Conditions/Comments
I
SOURCE
= 100 A with DV
DD
= 3 V. Except for MCLK OUT
12
Unipolar Mode
Bipolar Mode
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
For Specified Performance
For Specified Performance
AV
= 3 V or 5 V. BST Bit of Filter High Register 0
17
, CLKDIS = 1
Typically 0.22 mA. BUFFER = 0 V. f
CLK IN
= 1 MHz or 2.4576 MHz
Typically 0.45 mA. BUFFER = DV
= 1 MHz or 2.4576 MHz
AV
3 V or 5 V. BST Bit of Filter High Register =
Typically 0.38 mA. BUFFER = 0 V. f
CLK IN
= 2.4576 MHz
Typically 0.8 mA. BUFFER = DV
.
2.4576 MHz
Digital I/Ps = 0 V or DV
DD.
External MCLK IN, CLKDIS = 1
Typically 0.06 mA. DV
DD
= 3 V. f
CLK IN
= 1 MHz
Typically 0.13 mA. DV
DD
= 5 V. f
CLK IN
= 1 MHz
Typically 0.15 mA. DV
DD
= 3 V. f
CLK IN
= 2.4576 MHz
Typically 0.3 mA. DV
DD
= 5 V. f
CLK IN
= 2.4576 MHz
0.5
1.1
mA max
mA max
DV
DD
Current
18
0.080
0.16
0.18
0.35
See Note 20
mA max
mA max
mA max
mA max
dB typ
Power Supply Rejection
19
Normal-Mode Power Dissipation
18
AV
= DV
= +3 V. Digital I/Ps = 0 V or DV
DD
. External MCLK IN
BST Bit of Filter High Register 0
Typically 0.84 mW. BUFFER = 0 V. f
CLK IN
= 1 MHz. BST Bit = 0
Typically 1.53 mW. BUFFER = +3 V. f
CLK IN
= 1 MHz. BST Bit = 0
Typically 1.11 mW. BUFFER = 0 V. f
CLK IN
= 2.4576 MHz. BST Bit = 0
Typically 1.9 mW. BUFFER = +3 V. f
= 2.4576 MHz. BST Bit = 0
AV
= DV
= +5 V. Digital I/Ps = 0 V or DV
. External MCLK IN
Typically 1.75 mW. BUFFER = 0 V. f
CLK IN
= 1 MHz. BST Bit = 0
Typically 2.9 mW. BUFFER = +5 V. f
CLK IN
= 1 MHz. BST Bit = 0
Typically 2.6 mW. BUFFER = 0 V. f
= 2.4576 MHz. BST Bit = 0
Typically 3.75 mW. BUFFER = +5 V. f
CLK IN
= 2.4576 MHz. BST Bit = 0
External MCLK IN = 0 V or DV
DD
. Typically 9 A. V
DD
= +5 V
External MCLK IN = 0 V or DV
DD
. Typically 4 A. V
DD
= +3 V
1.05
2.04
1.35
2.34
mW max
mW max
mW max
mW max
Normal-Mode Power Dissipation
2.1
3.75
3.1
4.75
18
10
mW max
mW max
mW max
mW max
A max
A max
Standby Power-Down) Current
21
Standby Power-Down) Current
21