參數(shù)資料
型號： AD7712AR
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： LC2MOS Signal Conditioning ADC
中文描述： 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24
封裝： SOIC-24
文件頁數(shù)： 3/28頁
文件大?。?/td> 229K
代理商： AD7712AR
Parameter
REFERENCE OUTPUT
Output Voltage
Initial Tolerance
Drift
Output Noise
Line Regulation (AV
DD
)
Load Regulation
External Current
V
BIAS
INPUT
13
A, S Versions
1
Units
Conditions/Comments
2.5
±
1
20
30
1
1.5
1
V nom
% max
ppm/
°
C typ
μ
V typ
mV/V max
mV/mA max
mA max
pk-pk Noise; 0.1 Hz to 10 Hz Bandwidth
Maximum Load Current 1 mA
AV
– 0.85
×
V
REF
or AV
DD
– 3.5
See V
Input Section
Whichever Is Smaller; +5 V/–5 V or +10 V/0 V
Nominal AV
/V
Whichever Is Smaller; +5 V/0 V Nominal AV
DD
/V
SS
See V
Input Section
Whichever Is Greater; +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
Whichever Is Greater; +5 V/0 V Nominal AV
DD
/V
SS
Increasing with Gain
V max
or AV
– 2.1
V
+ 0.85
×
V
REF
or V
SS
+ 3
V max
V min
or V
SS
+ 2.1
65 to 85
V min
dB typ
V
BIAS
Rejection
LOGIC INPUTS
Input Current
All Inputs except MCLK IN
V
INL
, Input Low Voltage
V
, Input High Voltage
MCLK IN Only
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
LOGIC OUTPUTS
V
OL
, Output Low Voltage
V
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
14
TRANSDUCER BURNOUT
Current
Initial Tolerance
Drift
SYSTEM CALIBRATION
AIN1
Positive Full-Scale Calibration Limit
15
Negative Full-Scale Calibration Limit
15
Offset Calibration Limit
16, 17
Input Span
15
±
10
μ
A max
0.8
2.0
V max
V min
0.8
3.5
V max
V min
0.4
4.0
±
10
9
V max
V min
μ
A max
pF typ
I
SINK
= 1.6 mA
I
SOURCE
= 100
μ
A
4.5
±
10
0.1
μ
A nom
% typ
%/
°
C typ
(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
0.8
×
V
REF
/GAIN
(2.1
×
V
REF
)/GAIN
V max
V max
V max
V min
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
AIN2
Positive Full-Scale Calibration Limit
15
Negative Full-Scale Calibration Limit
15
Offset Calibration Limit
17
Input Span
15
(4.2
×
V
REF
)/GAIN
–(4.2
×
V
REF
)/GAIN
–(4.2
×
V
REF
)/GAIN
3.2
×
V
REF
/GAIN
(8.4
×
V
REF
)/GAIN
V max
V max
V max
V min
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
NOTES
13
The AD7712 is tested with the following V
voltages. With AV
DD
= +5 V and V
SS
= 0 V, V
BIAS
= +2.5 V; with AV
DD
= +10 V and V
SS
= 0 V, V
BIAS
= +5 V and
with AV
= +5 V and V
= –5 V, V
= 0 V.
14
Guaranteed by design, not production tested.
15
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
16
These calibration and span limits apply provided the absolute voltage on the AIN1 analog inputs does not exceed AV
DD
+ 30 mV or does not go more negative
than V
– 30 mV.
17
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
AD7712
–3–
REV. E
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