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參數(shù)資料
| 型號(hào)： | AD7712AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Signal Conditioning ADC |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁(yè)數(shù)： | 10/28頁(yè) |
| 文件大小： | 229K |
| 代理商： | AD7712AR |
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REV. E
–10–
AD7712
PGA Gain
G2
0
0
0
0
1
1
1
1
Channel Selection
CH
Channel
0
AIN1
1
AIN2
Power-Down
PD
0
Normal Operation
1
Power-Down
Word Length
WL
Output Word Length
0
16-Bit
1
24-Bit
Burnout Current
BO
0
Off
1
On
Bipolar/Unipolar Selection (Both Inputs)
B/U
0 Bipolar
1 Unipolar
Filter Selection (FS11–FS0)
The on-chip digital filter provides a Sinc
3
(or (Sinx/x)
3
) filter response. The 12 bits of data programmed into these bits determine
the filter cutoff frequency, the position of the first notch of the filter and the data rate for the part. In association with the gain selec-
tion, it also determines the output noise (and hence the effective resolution) of the device.
The first notch of the filter occurs at a frequency determined by the relationship: filter first notch frequency = (f
CLK IN
/512)/
code
where
code
is the decimal equivalent of the code in bits FS0 to FS11 and is in the range 19 to 2,000. With the nominal f
CLK IN
of
10 MHz, this results in a first notch frequency range from 9.76 Hz to 1.028 kHz. To ensure correct operation of the AD7712, the
value of the code loaded to these bits must be within this range. Failure to do this will result in unspecified operation of the device.
Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I and II and Figure 2 show the effect of
the filter notch frequency and gain on the effective resolution of the AD7712. The output data rate (or effective conversion time) for
the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at
50 Hz, then a new word is available at a 50 Hz rate or every 20 ms. If the first notch is at 1 kHz, a new word is available every 1 ms.
The settling time of the filter to a full-scale step input change is worst case 4
×
1/(output data rate). This settling time is to 100% of
the final value. For example, with the first filter notch at 50 Hz, the settling time of the filter to a full-scale step input change is
80 ms max. If the first notch is at 1 kHz, the settling time of the filter to a full-scale input step is 4 ms max. This settling time can be
reduced to 3
×
l/(output data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step
input takes place with
SYNC
low, the settling time will be 3
×
l/(output data rate). If a change of channels takes place, the settling
time is 3
×
l/(output data rate) regardless of the
SYNC
input.
The –3 dB frequency is determined by the programmed first notch frequency according to the relationship: filter –3 dB frequency
= 0.262
×
first notch frequency.
Gl
0
0
1
1
0
0
1
1
G0
0
1
0
1
0
1
0
1
Gain
1
2
4
8
16
32
64
128
(Default Condition After the Internal Power-On Reset)
Low Level Input
High Level Input
(Default Condition After the Internal Power-On Reset)
(Default Condition After the Internal Power-On Reset)
(Default Condition After Internal Power-On Reset)
(Default Condition After Internal Power-On Reset)
(Default Condition After Internal Power-On Reset)
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