參數(shù)資料
型號： AD7712AR
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： LC2MOS Signal Conditioning ADC
中文描述： 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24
封裝： SOIC-24
文件頁數(shù)： 2/28頁
文件大?。?/td> 229K
代理商： AD7712AR
Parameter
STATIC PERFORMANCE
No Missing Codes
A, S Versions
1
Units
Conditions/Comments
24
22
18
15
12
See Tables I & II
±
0.0015
±
0.003
See Note 4
1
0.3
See Note 4
0.5
0.25
See Note 4
0.5
0.25
2
±
0.003
±
0.006
1
0.3
Bits min
Bits min
Bits min
Bits min
Bits min
Guaranteed by Design. For Filter Notches
≤
60 Hz
For Filter Notch = 100 Hz
For Filter Notch = 250 Hz
For Filter Notch = 500 Hz
For Filter Notch = 1 kHz
Depends on Filter Cutoffs and Selected Gain
Filter Notches
≤
60 Hz
Typically
±
0.0003%
Excluding Reference
Excluding Reference. For Gains of 1, 2
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
Output Noise
Integral Nonlinearity @ +25
°
C
T
to T
Positive Full-Scale Error
2, 3
Full-Scale Drift
5
% FSR max
% FSR max
μ
V/
°
C typ
μ
V/
°
C typ
Unipolar Offset Error
2
Unipolar Offset Drift
5
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
Bipolar Zero Error
2
Bipolar Zero Drift
5
μ
V/
°
C typ
μ
V/
°
C typ
ppm/
°
C typ
% FSR max
% FSR max
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
Gain Drift
Bipolar Negative Full-Scale Error
2
@ +25
°
C
T
to T
Bipolar Negative Full-Scale Drift
5
Excluding Reference
Typically
±
0.0006%
Excluding Reference. For Gains of 1, 2
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
ANALOG INPUTS/REFERENCE INPUTS
Normal-Mode 50 Hz Rejection
6
Normal-Mode 60 Hz Rejection
6
AIN1/REF IN
DC Input Leakage Current
@ +25
°
C
6
T
to T
Sampling Capacitance
6
Common-Mode Rejection (CMR)
Common-Mode 50 Hz Rejection
6
Common-Mode 60 Hz Rejection
6
Common-Mode Voltage Range
7
Analog Inputs
8
Input Sampling Rate, f
S
AIN1 Input Voltage Range
9
100
100
dB min
dB min
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±
0.02
×
f
NOTCH
10
1
20
100
150
150
V
SS
to AV
DD
pA max
nA max
pF max
dB min
dB min
dB min
V min to V max
At DC
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±
0.02
×
f
NOTCH
See Table III
For Normal Operation. Depends on Gain Selected
Unipolar Input Range (B/U Bit of Control Register = 1)
Bipolar Input Range (B/U Bit of Control Register = 0)
For Normal Operation. Depends on Gain Selected
Unipolar Input Range (B/U Bit of Control Register = 1)
Bipolar Input Range (B/U Bit of Control Register = 0)
0 to +V
REF10
±
V
REF
V max
V max
AIN2 Input Voltage Range
9
0 to + 4
×
V
REF10
±
4
×
V
REF
30
±
0.05
1
10
20
V max
V max
k
% typ
ppm/
°
C typ
mV max
μ
V/
°
C typ
AIN2 DC Input Impedance
AIN2 Gain Error
AIN2 Gain Drift
AIN2 Offset Error
11
AIN2 Offset Drift
Reference Inputs
REF IN(+) – REF IN(–) Voltage
12
Additional Error Contributed by Resistor Attenuator
Additional Drift Contributed by Resistor Attenuator
Additional Error Contributed by Resistor Attenuator
+2.5 to +5
V min to V max
For Specified Performance. Part Is Functional with
Lower V
REF
Voltages
Input Sampling Rate, f
S
NOTES
1
Temperature range is as follows: A Version, –40
°
C to +85
°
C; S Version –55
°
C to +125
°
C. See also Note 18.
2
Applies after calibration at the temperature of interest.
3
Positive full-scale error applies to both unipolar and bipolar input ranges.
4
These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20
μ
V typical after self-calibration
or background calibration.
5
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6
These numbers are guaranteed by design and/or characterization.
7
This common-mode voltage range is allowed provided that the input voltage on AIN1(+) and AIN1(–) does not exceed AV
DD
+ 30 mV and V
SS
– 30 mV.
8
The AIN1 analog input presents a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum recommended
source resistance depends on the selected gain (see Tables IV and V).
9
The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(–) input. The input voltage range on the AIN2
input is with respect to AGND. The absolute voltage on the AIN1 input should not go more positive than AV
DD
+ 30 mV or more negative than V
SS
– 30 mV.
10
V
REF
= REF IN(+) – REF IN(–).
11
This error can be removed using the system calibration capabilities of the AD7712. This error is not removed by the AD7712’s self-calibration features. The offset
drift on the AIN2 input is 4 times the value given in the STATIC PERFORMANCE section.
12
The reference input voltage range may be restricted by the input voltage range requirement on the V
BIAS
input.
f
CLK IN
/256
–2–
REV. E
(AV
DD
= +5V
6
5%; DV
DD
= +5V
6
5%; V
SS
= 0V or –5 V
6
5%; REF IN(+) = +2.5V;
REF IN(–) = AGND; MCLK IN = 10MHz unless otherwise stated. All specifications T
MIN
to T
MAX
unless otherwise noted.)
AD7712–SPECIFICATIONS
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