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參數(shù)資料
| 型號(hào)： | AD7711ARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT RTD I SOURCE 24SOIC |
| 標(biāo)準(zhǔn)包裝： | 400 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 1.03k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 52.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 80°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極；1 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極 |
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2
REV.G
AD7711
–21–
Write Operation
Data can be written to either the control register or the calibra-
tion registers. In either case, the write operation is not affected
by the
DRDY line and does not have any effect on the status of
DRDY. A write operation to the control register or the calibra-
tion register must always write 24 bits.
Figure 11 shows a write operation to the AD7711. A0 deter-
mines whether a write operation transfers data to the control
register or to the calibration registers. This A0 signal must
remain valid for the duration of the serial write operation. The
falling edge of
TFS enables the internally generated SCLK
output. The serial data to be loaded to the AD7711 must be
valid on the rising edge of this SCLK signal. Data is clocked
into the AD7711 on the rising edge of the SCLK signal with the
MSB transferred first. On the last active high time of SCLK, the
LSB is loaded to the AD7711. Subsequent to the next falling
edge of SCLK, the SCLK output is turned off. (The timing dia-
gram in Figure 11 assumes a pull-up resistor on the SCLK line.)
External Clocking Mode
The AD7711 is configured for external clocking mode by tying
the MODE pin low. In this mode, SCLK of the AD7711 is config-
ured as an input, and an external serial clock must be provided to
this SCLK pin. This external clocking mode is designed for direct
interface to systems that provide a serial clock output that is syn-
chronized to the serial data output, including microcontrollers
such as the 80C51, 87C51, 68HC11, 68HC05, and most digital
signal processors.
Read Operation
As with self-clocking mode, data can be read from either the
output register, the control register, or the calibration registers.
A0 determines whether the data read accesses data from the
control register or from the output/calibration registers. This A0
signal must remain valid for the duration of the serial read
operation. With A0 high, data is accessed from either the output
register or from the calibration registers. With A0 low, data is
accessed from the control register.
The function of the
DRDY line is dependent only on the output
update rate of the device and the reading of the output data
register.
DRDY goes low when a new data-word is available in
the output data register. It is reset high when the last bit of data
(either the 16th bit or 24th bit) is read from the output register.
If data is not read from the output register, the
DRDY line
remains low. The output register continues to be updated at the
output update rate, but
DRDY will not indicate this. A read
from the device in this circumstance accesses the most recent
word in the output register. If a new data-word becomes avail-
able to the output register while data is being read from the
output register,
DRDY will not indicate this and the new data-
word will be lost to the user.
DRDY is not affected by reading
from the control register or the calibration register.
Data can be accessed from the output data register only when
DRDY is low. If RFS goes low while DRDY is high, no data
transfer will take place.
DRDY does not have any effect on reading
data from the control register or from the calibration registers.
t15
t17
t10
t9
t19
t18
t16
t14
MSB
LSB
SDATA (I)
SCLK (O)
TFS (I)
A0 (I)
Figure 11. Self-Clocking Mode, Control/Calibration Register Write Operation
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