參數(shù)資料
型號： AD7707BRU
廠商： Analog Devices Inc
文件頁數(shù)： 35/52頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 3CH 20-TSSOP
標準包裝： 75
位數(shù)： 16
采樣率（每秒）： 500
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應商設(shè)備封裝： 20-TSSOP
包裝： 管件
輸入數(shù)目和類型： 1 個單端，單極；1 個單端，雙極；2 個偽差分，單極；2 個偽差分，雙極
AD7707
Rev. B | Page 40 of 52
AD7707 TO 8XC51 INTERFACE
An interface circuit between the AD7707 and the 8XC51
microcontroller is shown in Figure 24. The diagram shows the
minimum number of interface connections with CS on the
AD7707 hard-wired low. In the case of the 8XC51 interface, the
minimum number of interconnects is just two. In this scheme,
the DRDY bit of the communications register is monitored to
determine when the data register is updated. The alternative
scheme, which increases the number of interface lines to three,
is to monitor the DRDY output line from the AD7707. The
monitoring of the DRDY line can be done in two ways. First,
DRDY can be connected to one of the 8XC51’s port bits (such as
P1.0), which is configured as an input. This port bit is then polled
to determine the status of DRDY. The second scheme is to use
an interrupt-driven system, in which case the DRDY output is
connected to the INT1 input of the 8XC51. For interfaces that
require control of the CS input on the AD7707, one of the port
bits of the 8XC51 (such as P1.1), which is configured as an output,
can be used to drive the CS input. The 8XC51 is configured in
its Mode 0 serial interface mode. Its serial interface contains a
single data line. As a result, the DATA OUT and DATA IN pins
of the AD7707 should be connected together with a 10 kΩ pull-
up resistor. The serial clock on the 8XC51 idles high between
data transfers. The 8XC51 outputs the LSB first in a write
operation; however, the AD7707 expects the MSB first so the
data to be transmitted must be rearranged before being written
to the output serial register. Similarly, the AD7707 outputs the MSB
first during a read operation; however, the 8XC51 expects the
LSB first. Therefore, the data read into the serial buffer must be
rearranged before the correct data word from the AD7707 is
available in the accumulator.
P3.0
P3.1
8XC51
RESET
SCLK
DOUT
DIN
CS
AD7707
VDD
08
69
1-
0
24
Figure 24. AD7707-to-8XC51 Interface
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