參數(shù)資料
型號(hào)： AD7707BRU
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/52頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT 3CH 20-TSSOP
標(biāo)準(zhǔn)包裝： 75
位數(shù)： 16
采樣率（每秒）： 500
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 1 個(gè)單端，單極；1 個(gè)單端，雙極；2 個(gè)偽差分，單極；2 個(gè)偽差分，雙極
AD7707
Rev. B | Page 21 of 52
Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 0x05
The clock register is an 8-bit register from which data can either be read or to which data can be written. Table 22 outlines the bit
designations for the clock register.
Table 22. Clock Register
Zero (0)
CLKDIS (0)
CLKDIV (0)
CLK (1)
FS2 (0)
FS1 (0)
FS0 (1)
Table 23. Clock Register Bit Descriptions
Bit
Description
Zero
Zero. A zero must be written to these bits to ensure correct operation of the AD7707. Failure to do so may result in unspecified
operation of the device.
CLKDIS
Master clock disable bit. A Logic 1 in this bit disables the master clock from appearing at the MCLK OUT pin. When disabled, the
MCLK OUT pin is forced low. This feature allows the user the flexibility of using the MCLK OUT as a clock source for other devices
in the system or of turning off the MCLK OUT as a power saving feature. When using an external master clock on the MCLK IN
pin, the AD7707 continues to have internal clocks and converts normally with the CLKDIS bit active. When using a crystal
oscillator or ceramic resonator across the MCLK IN and MCLK OUT pins, the AD7707 clock is stopped and no conversions take
place when the CLKDIS bit is active.
CLKDIV
Clock divider bit. With this bit at a Logic 1, the clock frequency appearing at the MCLK IN pin is divided by two before being used
internally by the AD7707. For example, when this bit is set to 1, the user can operate with a 4.9152 MHz crystal between MCLK
IN and MCLK OUT, and internally the part operates with the specified 2.4576 MHz. With this bit at a Logic 0, the clock frequency
appearing at the MCLK IN pin is the frequency used internally by the part.
CLK
Clock bit. This bit should be set in accordance with the operating frequency of the AD7707. If the device has a master clock
frequency of 2.4576 MHz (CLKDIV = 0) or 4.9152 MHz (CLKDIV = 1), then this bit should be set to a 1. If the device has a master
clock frequency of 1 MHz (CLKDIV = 0) or 2 MHz (CLKDIV = 1), this bit should be set to a 0. This bit sets up the appropriate scaling
currents for a given operating frequency and also chooses (along with FS2, FS1 and FS0) the output update rate for the device. If
this bit is not set correctly for the master clock frequency of the device, then the AD7707 may not operate to specification.
FS2, FS1,
FS0
Filter selection bits. Along with the CLK bit, FS2, FS1, and FS0 determine the output update rate, filter first notch, and 3 dB
frequency as outlined in Table 24. The on-chip digital filter provides a sinc3 (or Sinx/x3) filter response. Placing the first notch at
10 Hz places notches at both 50 Hz and 60 Hz, giving better than 150 dB rejection at these frequencies. In association with the
gain selection, the filter cutoff also determines the output noise of the device. Changing the filter notch frequency, as well as the
selected gain, impacts resolution. Table 7 to Table 13 show the effect of filter notch frequency and gain on the output noise and
effective resolution of the part. The output data rate (or effective conversion time) for the device is equal to the frequency
selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz, a new word is available at a
50 Hz output rate, or every 20 ms. If the first notch is at 500 Hz, a new word is available every 2 ms. A calibration should be
initiated when any of these bits are changed.
The settling time of the filter to a full-scale step input is worst-case 4 × 1/(output data rate). For example, with the filter first
notch at 50 Hz, the settling time of the filter to a full-scale step input is 80 ms maximum. If the first notch is at 500 Hz, the
settling time is 8 ms maximum. This settling time can be reduced to 3 × 1/(output data rate) by synchronizing the step input
change to a reset of the digital filter. In other words, if the step input takes place with the FSYNC bit high, the settling time is 3 ×
1/(output data rate) from when the FSYNC bit returns low.
The 3 dB frequency is determined by the programmed first notch frequency according to the following relationship:
filter 3 dB frequency = 0.262 × filter first notch frequency
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