參數資料
| 型號： | AD7660ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 9/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT UNIPOLAR 48LQFP |
| 標準包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數： | 16 |
| 采樣率（每秒）： | 100k |
| 數據接口： | 串行，并聯 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 25mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 2 個偽差分，單極 |
| 配用： | EVAL-AD7660CBZ-ND - BOARD EVALUATION FOR AD7660 |
REV. D
AD7660
–17–
External Clock Data Read during Conversion
Figure 20 shows the detailed timing diagrams of this method.
During a conversion, while both
CS and RD are LOW, the
result of the previous conversion can be read. The data is shifted
out, MSB first, with 16 clock pulses, and is valid on both the
rising and falling edges of the clock. The 16 bits have to be read
before the current conversion is complete; this, otherwise,
RDERROR is pulsed HIGH and can be used to interrupt the host
interface to prevent incomplete data reading. There is no daisy-
chain feature in this mode, and RDC/SDIN input should always
be tied either HIGH or LOW.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 18 MHz is recommended to ensure
that all the bits are read during the first half of the conversion
phase. For this reason, this mode is more difficult to use.
MICROPROCESSOR INTERFACING
The AD7660 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal pro-
cessing applications interfacing to a digital signal processor.
The AD7660 is designed to interface either with a parallel 8-bit or
16-bit wide interface, or with a general-purpose serial port or I/O
ports on a microcontroller. A variety of external buffers can be
used with the AD7660 to prevent digital noise from coupling
into the ADC. The following section discusses the use of an
AD7660 with an ADSP-219x SPI equipped DSP.
SDOUT
CS
SCLK
D1
D0
X
D15
D14
D13
12
3
14
15
16
t3
t35
t36 t37
t31
t32
t16
CNVST
BUSY
EXT/
INT = 1
INVSCLK = 0
RD = 0
Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
SPI Interface (ADSP-219x)
Figure 21 shows an interface diagram between the AD7660 and
an SPI-equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7660 acts as a slave device and data
must be read after conversion. This mode also allows the daisy-
chain feature. The convert command can be initiated in response
to an internal timer interrupt. The reading process cab be initi-
ated in response to the end-of-conversion signal (BUSY going
LOW) using an interrupt line of the DSP. The serial interface
(SPI) on the ADSP-219x is configured for master mode—
(MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit
(CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00— by
writing to the SPI control register (SPICLTx). To meet all
timing requirements, the SPI clock should be limited to 17
Mbps, which allows it to read an ADC result in less than 1
ms.
When a higher sampling rate is desired, use of one of the paral-
lel interface modes is recommended.
SPIxSEL (PFx)
ADSP-219x*
CNVST
AD7660*
CS
BUSY
MISOx
SCKx
PFx or TFSx
SDOUT
SCLK
RD
INVSCLK
EXT/
INT
SER/
PAR
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
PFx
Figure 21. Interfacing the AD7660 to an SPI Interface
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