TMIN
參數(shù)資料
型號： AD7660ASTZRL
廠商： Analog Devices Inc
文件頁數(shù)： 14/20頁
文件大小： 0K
描述： IC ADC 16BIT UNIPOLAR 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 100k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 25mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個偽差分，單極
配用： EVAL-AD7660CBZ-ND - BOARD EVALUATION FOR AD7660
REV. D
–3–
AD7660
Parameter
Conditions
Min
Typ
Max
Unit
TEMPERATURE RANGE
Specified Performance
TMIN to TMAX
–40
+85
∞C
NOTES
1LSB means least significant bit. With the 0 V to 2.5 V input range, one LSB is 38.15
mV.
2Typical rms noise at worst-case transitions and temperatures.
3See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
4All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
5Tested in Parallel Reading Mode.
6With all digital inputs forced to DVDD or DGND respectively.
Specifications subject to change without notice.
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
REFER TO FIGURES 11 AND 12
Convert Pulsewidth
t1
5ns
Time between Conversions
t2
10
ms
CNVST LOW to BUSY HIGH Delay
t3
15
ns
BUSY HIGH All Modes Except in
t4
2
ms
Master Serial Read after Convert Mode
Aperture Delay
t5
2ns
End of Conversion to BUSY LOW Delay
t6
10
ns
Conversion Time
t7
2
ms
Acquisition Time
t8
8
ms
RESET Pulsewidth
t9
10
ns
REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t10
2
ms
DATA Valid to BUSY LOW Delay
t11
45
ns
Bus Access Request to DATA Valid
t12
40
ns
Bus Relinquish Time
t13
515
ns
REFER TO FIGURE 16 AND 17 (Master Serial Interface Modes)
1
CS LOW to SYNC Valid Delay
t14
10
ns
CS LOW to Internal SCLK Valid Delay
t15
10
ns
CS LOW to SDOUT Delay
t16
10
ns
CNVST LOW to SYNC Delay
t17
500
ns
SYNC Asserted to SCLK First Edge Delay
t18
4ns
Internal SCLK Period
t19
40
75
ns
Internal SCLK HIGH (INVSCLK Low)
2
t20
30
ns
Internal SCLK LOW (INVSCLK Low)
2
t21
9.5
ns
SDOUT Valid Setup Time
t22
4.5
ns
SDOUT Valid Hold Time
t23
3ns
SCLK Last Edge to SYNC Delay
t24
3
CS HIGH to SYNC HI-Z
t25
10
ns
CS HIGH to Internal SCLK HI-Z
t26
10
ns
CS HIGH to SDOUT HI-Z
t27
10
ns
BUSY HIGH in Master Serial Read after Convert
t28
3.2
ms
CNVST LOW to SYNC Asserted Delay
t29
1.5
ms
SYNC Deasserted to BUSY LOW Delay
t30
50
ns
REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)
1
External SCLK Setup Time
t31
5ns
External SCLK Active Edge to SDOUT Delay
t32
316
ns
SDIN Setup Time
t33
5ns
SDIN Hold Time
t34
5ns
External SCLK Period
t35
25
ns
External SCLK HIGH
t36
10
ns
External SCLK LOW
t37
10
ns
NOTES
1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L of 10 pF; otherwise, the load is 60 pF maximum.
2If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
Specifications subject to change without notice.
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