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參數(shù)資料
| 型號： | AD7660ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT UNIPOLAR 48LQFP |
| 標準包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 25mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個偽差分，單極 |
| 配用： | EVAL-AD7660CBZ-ND - BOARD EVALUATION FOR AD7660 |
REV. D
AD7660
–6–
PIN FUNCTION DESCRIPTIONS (continued)
Pin
No.
Mnemonic
Type
Description
22
D9
DI/O
When SER/
PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
or SCLK
When SER/
PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/
INT pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
23
D10
DO
When SER/
PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
or SYNC
When SER
/PAR is HIGH, this output, part of the Serial Port, is used as a digital output
frame synchronization for use with the internal data clock (EXT/
INT = Logic LOW). When
a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains
HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is
HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid.
24
D11
DO
When SER/
PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus.
or RDERROR
When SER/
PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is
used as an incomplete read error flag. In Slave Mode, when a data read is started and not
complete when the following conversion is complete, the current data is lost and RDERROR is
pulsed HIGH.
25–28
D[12:15]
DO
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regard-
less of the state of SER/
PAR.
29
BUSY
DO
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data-ready clock signal.
30
DGND
P
Must Be Tied to Digital Ground
31
RD
DI
Read Data. When
CS and RD are both LOW, the interface parallel or serial output bus is
enabled.
32
CS
DI
Chip Select. When
CS and RD are both LOW, the interface parallel or serial output bus is
enabled.
CS is also used to gate the external clock.
33
RESET
DI
Reset Input. When set to a logic HIGH, reset the AD7660. Current conversion, if any, is aborted.
34
PD
DI
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver-
sions are inhibited after the current one is completed.
35
CNVST
DI
Start Conversion. If
CNVST is HIGH when the acquisition phase (t
8) is complete, the next
falling edge on
CNVST puts the internal sample-and-hold into the hold state and initiates a
conversion. This mode is the most appropriate if low sampling jitter is desired. If
CNVST is
LOW when the acquisition phase (t8) is complete, the internal sample-and-hold is put into the
hold state and a conversion is immediately started.
36
AGND
P
Must Be Tied to Analog Ground
37
REF
AI
Reference Input Voltage
38
REFGND
AI
Reference Input Analog Ground
39
INGND
AI
Analog Input Ground
43
IN
AI
Primary Analog Input with a Range of 0 V to VREF
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
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