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參數(shù)資料
| 型號： | AD7654ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Dual 2-Channel Simultaneous Sampling SAR 500 kSPS 16-Bit ADC |
| 中文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026-BBC, LQFP-48 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大小： | 734K |
| 代理商： | AD7654ASTRL |
REV. 0
–6–
AD7654
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Type
Description
1, 47, 48
2
3
AGND
AVDD
A0
P
P
DI
Analog Power Ground Pin
Input Analog Power Pin. Nominally 5 V.
Multiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simul-
taneously, then converted. When HIGH, the analog inputs INA2 and INB2 are sampled
simultaneously, then converted.
Parallel Mode Selection (8 Bit, 16 Bit). When LOW, the LSB is output on D[7:0]
and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and
the MSB is output on D[7:0].
Data Channel Selection. In parallel mode, when LOW, the data from channel B is
read. When HIGH, the data from channel A is read. In serial mode, when HIGH,
channel A is output first followed by channel B. When LOW, channel B is output
first followed by channel B.
Digital Power Ground
Mode Selection. When HIGH, this input selects a reduced power mode. In this mode,
the power dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/
PAR
is HIGH, these
outputs are in high impedance.
When SER/
PAR
is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port
Data Output Bus.
When SER/
PAR
is HIGH, EXT/
INT
is LOW, and RDC/SDIN is LOW, which is the
serial master read after convert mode, these inputs, part of the serial port, are used to
slow down if desired the internal serial clock that clocks the data output. In the other
serial modes, these inputs are not used.
When SER/
PAR
is LOW, this output is used as Bit 4 of the Parallel Port Data
Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used as a digital select
input for choosing the internal or an external data clock, called respectively, Master
and Slave Mode. With EXT/INT tied LOW, the internal clock is selected on SCLK
output. With EXT/INT set to a logic HIGH, output data is synchronized to an external
clock signal connected to the SCLK input.
4
BYTESWAP
DI
5
A/
B
DI
6, 20
7
DGND
IMPULSE
P
DI
8
SER/
PAR
DI
9, 10
D[0:1]
DO
11, 12
D[2:3] or
DI/O
DIVSCLK[0:1]
13
D[4]
DI/O
or EXT/INT
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
TOP VIEW
(Not to Scale)
DVDD
CNVST
PD
RESET
CS
RD
EOC
BUSY
D15
D14
D13
D12
AGND
AVDD
A0
BYTESWAP
A/
B
DGND
IMPULSE
SER/
PAR
D0
D1
D2/DIVSCLK[0]
D3/DIVSCLK[1]
AD7654
A
A
I
I
I
R
R
I
I
I
R
R
D
I
D
D
D
O
O
D
D
D
D
D
D
PIN CONFIGURATION
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| AD7654ASTZ | 功能描述:IC ADC 16BIT 500KSPS DUAL 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7654ASTZ | 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7654 LQFP48 |
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