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參數(shù)資料
| 型號： | AD7654ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Dual 2-Channel Simultaneous Sampling SAR 500 kSPS 16-Bit ADC |
| 中文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026-BBC, LQFP-48 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 734K |
| 代理商： | AD7654ASTRL |
REV. 0
–16–
AD7654
t
1
t
3
t
4
t
17
CNVST
BUSY
DATA BUS
CS
=
RD
= 0
t
16
NEW A
OR B
EOC
PREVIOUS CHANNEL A
OR B
PREVIOUS CHANNEL B
OR NEW A
t
10
Figure 10. Master Parallel Data Timing for Read-
ing (Continuous Read)
DATA BUS
t
18
t
19
BUSY
CS
RD
CURRENT
CONVERSION
Figure 11. Slave Parallel Data Timing for Reading
(Read after Convert)
PREVIOUS
CONVERSION
t
1
t
3
t
18
t
19
t
4
CS
= 0
CNVST
,
RD
BUSY
DATA BUS
EOC
t
13
t
11
t
12
t
10
Figure 12. Slave Parallel Data Timing for Reading
(Read during Convert)
PARALLEL INTERFACE
The AD7654 is configured to use the parallel interface (Figure 10)
when the SER/
PAR
is held low. The data can be read either
after each conversion, which is during the next acquisition phase
or during the other channel’s conversion, or during the following
conversion as shown, respectively, in Figures 11 and 12. When the
data is read during the conversion, however, it is recommended
that it is read only during the first half of the conversion
phase. This avoids any potential feedthrough between voltage
transients on the digital interface and the most critical analog
conversion circuitry.
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 13, the LSB byte is output on D[7:0] and
the MSB is output on D[15:8] when BYTESWAP is low. When
BYTESWAP is high, the LSB and MSB bytes are swapped, the
LSB is output on D[15:8], and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].
CS
RD
BYTE
PINS D[15:8]
PINS D[7:0]
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
LOW BYTE
HIGH BYTE
HI-Z
HI-Z
t
18
t
18
t
19
Figure 13. 8-Bit Parallel Interface
CS
A/
B
RD
HI-Z
CHANNEL A
t
18
DATA BUS
t
20
CHANNEL B
HI-Z
Figure 14. A/
B
Channel Reading
The detailed functionality of A/
B
is explained in Figure 15.
When high, the data from channel A is available on the data bus.
When low, the data bus now carries output from channel B.
Note that channel A can be read immediately after conversion is
done (
EOC
), while channel B is still in its converting phase.
SERIAL INTERFACE
The AD7654 is configured to use the serial interface when the
SER/PAR is held high. The AD7654 outputs 32 bits of data,
MSB first, on the SDOUT pin. The order of the channels being
output is controlled by A/B. When high, channel A is output
first; when low, channel B is output first. Unlike in parallel
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| AD7654ASTZ | 功能描述:IC ADC 16BIT 500KSPS DUAL 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7654ASTZ | 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7654 LQFP48 |
| AD7654ASTZRL | 功能描述:IC ADC 16BIT DUAL 2CH 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7655 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 1 MSPS, Differential, Programmable Input PulSAR ADC |
| AD7655ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:LOW COST 4-CHANNEL 1 MSPS 16-BIT ADC - Bulk 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7655 LFSCP-48 |
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