參數(shù)資料
型號(hào)： AD7625BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/24頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT 6MSPS SAR 32LFCSP
設(shè)計(jì)資源： High Speed, Precision, Differential AC-Coupled Drive Circuit for AD7625 (CN0080)
特色產(chǎn)品： AD7625: 16-Bit, 6MSPS PulSAR Differential ADC
標(biāo)準(zhǔn)包裝： 1
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 6M
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 190mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 托盤
輸入數(shù)目和類型： 1 個(gè)差分，雙極
Data Sheet
AD7625
Rev. A | Page 21 of 24
APPLICATIONS INFORMATION
LAYOUT, DECOUPLING, AND GROUNDING
When laying out the printed circuit board (PCB) for the AD7625,
follow the practices described in this section to obtain the maxi-
mum performance from the converter.
Exposed Paddle
The AD7625 has an exposed paddle on the underside of the
package.
Solder the paddle directly to the PCB.
Connect the paddle to the ground plane of the board using
multiple vias, as shown in Figure 31.
Decouple all supply pins except for Pin 12 (VIO) directly to
the paddle, minimizing the current return path.
Pin 13 and Pin 24 can be connected directly to the paddle.
Use vias to ground at the point where these pins connect to
the paddle.
VDD1 Supply Routing and Decoupling
The VDD1 supply is connected to Pin 1, Pin 19, and Pin 20. The
supply should be decoupled using a 100 nF capacitor at Pin 1.
The user can connect this supply trace to Pin 19 and Pin 20. Use
a series ferrite bead to connect the VDD1 supply from Pin 1 to
Pin 19 and Pin 20. The ferrite bead isolates any high frequency
noise or ringing on the VDD1 supply. Decouple the VDD1
supply to Pin 19 and Pin 20 using a 100 nF capacitor to GND.
This GND connection can be placed a short distance away from
the exposed paddle.
VIO Supply Decoupling
Decouple the VIO supply applied to Pin 12 to ground at Pin 13.
Layout and Decoupling of Pin 25 to Pin 32
Connect the outputs of Pin 25, Pin 26, and Pin 28 together and
decouple them to Pin 27 using a 10 μF capacitor with low ESR
and low ESL.
Reduce the inductance of the path connecting Pin 25, Pin 26,
and Pin 28 by widening the PCB traces connecting these pins.
A similar approach should be taken in the connections used for
the reference pins of the AD7625. Connect Pin 29, Pin 30, and
Pin 32 together using widened PCB traces to reduce inductance.
In internal or external reference mode, a 4.096 V reference voltage
is output on Pin 29, Pin 30, and Pin 32. Decouple these pins to
Pin 31 using a 10 μF capacitor with low ESR and low ESL.
Figure 31 shows an example of the recommended layout for
the underside of the AD7625 device. Note the extended signal
trace connections and the outline of the capacitors decoupling
the signals applied to the REF pins (Pin 29, Pin 30, and Pin 32)
and to the CAP2 pins (Pin 25, Pin 26, and Pin 28).
32
31
30
29
28
27
26
25
Paddle
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24 23 22 21 20 19 18 17
4.096V
EXTERNAL REFERENCE
(ADR434 OR ADR444)
07652-
013
Figure 31. PCB Layout and Decoupling Recommendations for Pin 24 to Pin 32
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