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參數(shù)資料
| 型號： | AD7625BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 6MSPS SAR 32LFCSP |
| 設(shè)計資源： | High Speed, Precision, Differential AC-Coupled Drive Circuit for AD7625 (CN0080) |
| 特色產(chǎn)品： | AD7625: 16-Bit, 6MSPS PulSAR Differential ADC |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 6M |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 190mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
AD7625
Data Sheet
Rev. A | Page 20 of 24
Self-Clocked Interface Mode
The digital operation of the AD7625 in self-clocked interface
mode is shown in Figure 30. This interface mode reduces the
number of wires between ADCs and the digital host to two LVDS
pairs per AD7625 (CLK± and D±) or to a single pair if sharing a
common CLK± using multiple AD7625 devices. Self-clocked
interface mode facilitates the design of boards that use multiple
AD7625 devices. The digital host can adapt the interfacing
scheme to account for differing propagation delays between
each AD7625 device and the digital host.
The self-clocked interface mode consists of preceding the results
of each ADC word with a 2-bit header on the data, D±. This
header is used to synchronize D± of each conversion in the
digital host. Synchronization is accomplished by one simple
state machine per AD7625 device. For example, if the state
machine is running at the same speed as CLK± with three
phases, the state machine measures when the Logic 1 of the
header occurs.
Conversions are initiated by a CNV± pulse. The CNV± pulse
must be returned low (≤tCNVH maximum) for valid operation.
After a conversion begins, it continues until completion. Addi-
tional CNV± pulses are ignored during the conversion phase.
After the time tMSB elapses, the host should begin to burst the
CLK±. Note that tMSB is the maximum time for the first bit of
the header and should be used as the gating device for CLK±.
CLK± is also used internally on the host to begin the internal
synchronization state machine. The next header bit and conversion
results are output on subsequent falling edges of CLK±. The
only requirement is that the 18 CLK± pulses finish before the
time tCLKL elapses for the next conversion phase or the data is
lost. Set CLK± to idle high between bursts of 18 CLK± pulses.
CLK+
18
17
1
4
2
1
2
3
tCLKL
D+
D–
CLK–
D0
N – 1
D1
N – 1
ACQUISITION
tCLKD
tCLK
tMSB
18
17
3
D15
N
D14
N
D1
N
0
1
D0
N
D15
N + 1
0
1
tCYC
CNV+
tCNVH
SAMPLE N
SAMPLE N + 1
CNV–
tACQ
07652-
004
Figure 30. Self-Clocked Interface Mode Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7625BCPZRL7 | 功能描述:IC ADC 16BIT 6MSPS SAR 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7626 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 10 MSPS, PulSAR Differential ADC |
| AD7626_09 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 10 MSPS, PulSAR Differential ADC |
| AD7626_10 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 10 MSPS, PulSAR Differential ADC |
| AD7626BCPZ | 功能描述:IC ADC 16BIT 10MSPS DIFF 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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