參數(shù)資料
型號： AD7621ACPZ
廠商： Analog Devices Inc
文件頁數(shù)： 2/32頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 2MSPS DIFF 48LFCSP
標準包裝： 1
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 2M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 86mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤
輸入數(shù)目和類型： 1 個差分，雙極
AD7621
Rev. 0 | Page 10 of 32
Pin No.
Mnemonic
Description
32
CS
DI
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock in slave serial mode.
33
RESET
DI
Reset Input. When high, reset the AD7621. Current conversion if any is aborted. Falling edge of RESET
enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface section. If
not used, this pin can be tied to DGND.
34
PD
DI
Power-Down Input. When high, power down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed.
35
CNVST
DI
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.
36
AGND
P
Analog Power Ground Pin.
37
REF
AI/O
Reference Output/Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally
supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal
reference and buffer. Refer to the Voltage Reference Input section.
38
REFGND
AI
Reference Input Analog Ground.
39
IN
AI
Differential Negative Analog Input.
43
IN+
AI
Differential Positive Analog Input.
45
TEMP
AO
Temperature Sensor Analog Output.
46
REFBUFIN
AI/O
Internal Reference Output/Reference Buffer Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V
(typical) bandgap output on this pin, which needs external decoupling. The internal fixed gain
reference buffer uses this to produce 2.048V on the REF pin.
When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high),
applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section.
47
PDREF
DI
Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down and an external reference must been used.
48
PDBUF
DI
Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
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