Limit at TMIN, T
參數(shù)資料
型號(hào): AD7606BSTZ-4RL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 36/36頁(yè)
文件大小: 0K
描述: IC DAS W/ADC 16BIT 64LQFP
設(shè)計(jì)資源: Layout Considerations for an Expandable Multichannel Simultaneous Sampling Data Acquisition System Based on AD7606 (CN0148)
標(biāo)準(zhǔn)包裝: 1
類型: 數(shù)據(jù)采集系統(tǒng)(DAS),ADC
分辨率(位): 16 b
采樣率(每秒): 200k
數(shù)據(jù)接口: DSP,MICROWIRE?,并聯(lián),QSPI?,串行,SPI?
電壓電源: 模擬和數(shù)字
電源電壓: 2.3 V ~ 5.25 V,4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AD7606BSTZ-4RLDKR
Data Sheet
AD7606/AD7606-6/AD7606-4
Rev. C | Page 9 of 36
Limit at TMIN, TMAX
(0.1 × VDRIVE and
0.9 × VDRIVE
Logic Input Levels)
Limit at TMIN, TMAX
(0.3 × VDRIVE and
0.7 × VDRIVE
Logic Input Levels)
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Description
t27
Delay from RD falling edge to FRSTDATA low
19
22
ns
VDRIVE = 3.3 V to 5.25V
24
29
ns
VDRIVE = 2.3 V to 2.7V
t28
Delay from 16th SCLK falling edge to FRSTDATA low
17
20
ns
VDRIVE = 3.3 V to 5.25V
22
27
ns
VDRIVE = 2.3 V to 2.7V
t29
24
29
ns
Delay from CS rising edge until FRSTDATA three-
state enabled
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2
In oversampling mode, typical tCONV for the AD7606-6 and AD7606-4 can be calculated using ((N × tCONV) + ((N 1) × 1 s)). N is the oversampling ratio. For the AD7606-6,
tCONV = 3 s; and for the AD7606-4, tCONV = 2 s.
3
The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets.
4
A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
Timing Diagrams
tCYCLE
t3
t5
t2
t4
t1
t7
tRESET
tCONV
CONVST A,
CONVST B
CONVST A,
CONVST B
BUSY
CS
RESET
08479-
002
Figure 2. CONVST Timing—Reading After a Conversion
tCYCLE
t3
t5
t6
t2
t1
tCONV
CONVST A,
CONVST B
CONVST A,
CONVST B
BUSY
CS
t7
tRESET
RESET
08479-
003
Figure 3. CONVST Timing—Reading During a Conversion
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