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參數(shù)資料
| 型號(hào)： | AD7568 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Octal 12-Bit DAC(LC2MOS八通道12位D/A轉(zhuǎn)換器) |
| 中文描述： | 八通道12位DAC（LC2MOS八通道12位的D / A轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 251K |
| 代理商： | AD7568 |
AD7568
REV. B
–11–
PC5
PC6
PC7
SCK
MOSI
CLKIN
SDIN
CLR
LDAC
FSIN
68HC11*
AD7568*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. AD7568 to 68HC11 Interface
In Figure 21,
LDAC
and
CLR
are controlled by the PC6 and
PC5 port outputs. As with the 80C51, each DAC of the
AD7568 can be updated after each two-byte transfer, or else all
DACs can be simultaneously updated.
AD7568–ADSP-2101 Interface
Figure 22 shows a serial interface between the AD7568 and the
ADSP-2101 digital signal processor. T he ADSP-2101 may be
set up to operate in the SPORT T ransmit Normal Internal
Framing Mode. T he following ADSP-2101 conditions are rec-
ommended: Internal SCLK ; Active High Framing Signal; 16-bit
word length. T ransmission is initiated by writing a word to the
T X register after the SPORT has been enabled. T he data is then
clocked out on every rising edge of SCLK after T FS goes low.
T FS stays low until the next data transfer.
FO
TFS
DT
SCLK
CLKIN
SDIN
CLR
LDAC
FSIN
ADSP-2101*
AD7568*
*ADDITIONAL PINS OMITTED FOR CLARITY
+5V
Figure 22. AD7568 to ADSP-2101 Interface
AD7568–T MS320C25 Interface
Figure 23 shows an interface circuit for the T MS320C25
digital signal processor. T he data on the DX pin is clocked
out of the processor’s T ransmit Shift Register by the CL K X
signal. Sixteen-bit transmit format should be chosen by setting
the FO bit in the ST 1 register to 0. T he transmit operation be-
gins when data is written into the data transmit register of the
T MS320C25. T his data will be transmitted when the FSX line
goes low while CLK X is high or going high. T he data, starting
XF
FSX
DX
CLKX
CLKIN
SDIN
CLR
LDAC
FSIN
TMS320C25*
AD7568*
*ADDITIONAL PINS OMITTED FOR CLARITY
+5V
CLOCK
GENERATION
Figure 23. AD7568 to TMS320C25 Interface
with the MSB, is then shifted out to the DX pin on the rising
edge of CLK X . When all bits have been transmitted, the user
can update the DAC outputs by bringing the X F output flag low.
Multiple DAC Systems
If there are only two AD7568s in a system, there is a simple way
of programming each. T his is shown in Figure 24. If the user
wishes to program one of the DACs in the first AD7568, then
DB3 of the serial bit stream should be set to 0, to correspond to
the state of the A0 pin on that device. If the user wishes to pro-
gram a DAC in the second AD7568, then DB3 should be set to
1, to correspond to A0 on that device.
FO
TFS
DT
SCLK
CLKIN
SDIN
CLR
LDAC
FSIN
ADSP-2101*
AD7568*
*ADDITIONAL PINS OMITTED FOR CLARITY
+5V
A0
CLKIN
SDIN
CLR
LDAC
FSIN
AD7568*
+5V
A0
Figure 24. Interfacing ADSP-2101 to Two AD7568s
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