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參數(shù)資料
| 型號(hào)： | AD7485 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 1 MSPS, Serial 14-Bit SAR ADC |
| 中文描述： | 1 MSPS的，串行14位SAR ADC |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 769K |
| 代理商： | AD7485 |
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REV. 0
AD7485
–5–
PIN FUNCTION DESCRIPTIONS
Pin
No.
1, 5, 13, 46
2
Mnemonic
AV
DD
C
BIAS
Description
Positive Power Supply for Analog Circuitry
Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin
and AGND.
Power Supply Ground for Analog Circuitry
3, 4, 6, 11, 12,
14, 15, 47, 48
7
8
AGND
VIN
REFOUT
Analog Input. Single-ended analog input channel.
Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470nF
capacitor must be placed between this pin and AGND.
Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using
an external voltage reference source, the reference voltage should be applied to this pin.
Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected
from this pin to AGND. When using an external reference source, this pin should be connected
directly to AGND.
Standby Logic Input. When this pin is logic high, the device will be placed in STANDBY mode.
See the Power Saving section for further details.
Nap Logic Input. When this pin is logic high, the device will be placed in a very low power mode.
See the Power Saving section for further details.
Master Clock Input. This is the input for the master clock, which controls the conversion cycle. The fre-
quency of this clock may be up to 25 MHz. Twenty-four clock cycles are required for each conversion.
Ground Reference for Digital Circuitry
9
REFIN
10
REFSEL
16
STBY
17
NAP
18
MCLK
19, 20, 22
–
28
30, 31, 33, 34
37
–
39, 43, 44
21
DGND
SDO
Serial Data Output. The conversion data is latched out on this pin on the rising edge of SCO. It
should be latched into the receiving serial port of the DSP on the falling edge of SCO. The over-
range bit is latched out first, then 14 bits of data (MSB first) followed by a trailing zero.
Positive Power Supply for Digital Circuitry
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
logic of the AD7485 will operate.
Transmit Frame Sync Input. In Serial Mode 2, this pin acts as a framing signal for the serial data
being clocked out on SDO. A falling edge on
TFS
brings SDO out of three-state and the data starts
to get clocked out on the next rising edge of SCO.
Serial Mode Input. A logic low on this pin selects Serial Mode 1 and a logic high selects Serial
Mode 2. See the Serial Interface section for further details.
Serial Clock Output. This clock is derived from MCLK and is used to latch conversion data from
the device. See the Serial Interface section for further details.
Convert Start Logic Input. A conversion is initiated on the falling edge of the
CONVST
signal. The
input track/hold amplifier goes from track mode to hold mode and the conversion process commences.
Reset Logic Input. A falling edge on this pin resets the internal state machine and terminates a
conversion that may be in progress. Holding this pin low keeps the part in a reset state.
29, 45
32
DV
DD
V
DRIVE
35
TFS
36
SMODE
40
SCO
41
CONVST
42
RESET
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| AD7485BSTZ | 功能描述:IC ADC 14BIT SAR 1MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7490 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP |
| AD7490_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP |
| AD7490BCP | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Serial 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:12 BIT 16 CHANNEL ADC IC - Bulk 制造商:Analog Devices 功能描述:IC 12-BIT ADC |
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