參數(shù)資料
型號(hào)： AD7485
廠商： AMIC Technology Corporation
英文描述： 1 MSPS, Serial 14-Bit SAR ADC
中文描述： 1 MSPS的，串行14位SAR ADC
文件頁(yè)數(shù)： 3/16頁(yè)
文件大?。?/td> 769K
代理商： AD7485
REV. 0
AD7485
–3–
Parameter
Specification
Unit
Test Conditions/Comments
POWER REQUIREMENTS
V
DD
V
DRIVE
5
2.7
5.25
V
V min
V max
±
5%
I
DD
Normal Mode (Static)
Normal Mode (Operational)
NAP Mode
STANDBY Mode
8
12
16
0.6
2
0.5
mA max
mA max
mA max
μ
A max
μ
A typ
Power Dissipation
Normal Mode (Operational)
NAP Mode
STANDBY Mode
8
80
3
10
mW max
mW max
μ
W max
NOTES
1
Temperature ranges as follows:
–
40
°
C to +85
°
C.
2
SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB.
3
See Typical Performance Characteristics section for analog input circuits used.
4
See Terminology.
5
Sample tested @ 25
°
C to ensure compliance.
6
Current drawn from external reference during conversion.
7
I
= 200
μ
A.
8
Digital input levels at GND or V
DRIVE
.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1
(V
DD
= 5 V
5%, AGND = DGND = 0 V, V
REF
= External; all specifications T
MIN
to T
MAX
and
valid for V
DRIVE
= 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Unit
Master Clock Frequency
MCLK Period
Conversion Time
CONVST
Low Period (Mode 1)
2
CONVST
High Period (Mode 1)
2
MCLK High Period
MCLK Low Period
CONVST
Falling Edge to MCLK Rising Edge
MCLK Rising Edge to MSB Valid
Data Valid before SCO Falling Edge
Data Valid after SCO Falling Edge
CONVST
Rising Edge to SDO Three-State
CONVST
Low Period (Mode 2)
2
CONVST
High Period (Mode 2)
3
CONVST
Falling Edge to
TFS
Falling Edge
TFS
Falling Edge to MSB Valid
TFS
Rising Edge to SDO Three-State
TFS
Low Period
4
TFS
High Period
4
MCLK Fall Time
MCLK Rise Time
MCLK
–
SCO Delay
f
MCLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
0.01
40
t
1
24
t
1
22
10
0.4 t
1
0.4 t
1
7
25
100000
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.6 t
1
0.6 t
1
15
10
20
6
t
1
2
10
10
10
30
8
t
1
22
10
5
5
6
25
25
25
NOTES
1
All timing specifications given above are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used.
2
CONVST
idling high. See Serial Interface section for further details.
3
CONVST
idling low. See Serial Interface section for further details.
4
TFS
can also be tied low in this mode.
Specifications subject to change without notice.
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