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參數(shù)資料
| 型號： | AD7468BRTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 1.6V LP SOT23-6 |
| 標準包裝： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 900µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-6 |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 產(chǎn)品目錄頁面： | 777 (CN2011-ZH PDF) |
| 其它名稱： | AD7468BRTZREEL7DKR |
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AD7466/AD7467/AD7468
Rev. C | Page 17 of 28
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7466/AD7467/AD7468 are fast, micropower, 12-bit,
10-bit, and 8-bit ADCs, respectively. The parts can be operated
from a 1.6 V to 3.6 V supply. When operated from any supply
voltage within this range, the AD7466/AD7467/AD7468 are
capable of throughput rates of 200 kSPS when provided with a
3.4 MHz clock.
The AD7466/AD7467/AD7468 provide the user with an on-
chip track-and-hold, an ADC, and a serial interface housed in a
tiny 6-lead SOT-23 or an 8-lead MSOP package, which offer the
user considerable space-saving advantages over alternative
solutions. The serial clock input accesses data from the part, but
also provides the clock source for the successive approximation
ADC. The analog input range is 0 V to VDD. An external refer-
ence is not required for the ADC, and there is no on-chip
reference. The reference for the AD7466/AD7467/AD7468 is
derived from the power supply, thus giving the widest possible
dynamic input range.
The AD7466/AD7467/AD7468 also feature an automatic
power-down mode to allow power savings between conversions.
The power-down feature is implemented across the standard
serial interface, as described in the Normal Mode section.
CONVERTER OPERATION
The AD7466/AD7467/AD7468 are successive approximation
analog-to-digital converters based around a charge redistribu-
of the ADC. Figure 19 shows the ADCs during the acquisition
phase. SW2 is closed and SW1 is in Position A, the comparator
is held in a balanced condition, and the sampling capacitor
acquires the signal on VIN.
SW2
SAMPLING
CAPACITOR
ACQUISITION
PHASE
COMPARATOR
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
SW1
A
B
AGND
VIN
VDD/2
02643-020
Figure 19. ADC Acquisition Phase
When the ADC starts a conversion, as shown in Figure 20,
SW2 opens and SW1 moves to Position B, causing the com-
parator to become unbalanced. The control logic and the
charge redistribution DAC are used to add and subtract fixed
amounts of charge from the sampling capacitor to bring the
comparator back into a balanced condition. When the com-
parator is rebalanced, the conversion is complete. The control
logic generates the ADC output code. Figure 21 shows the ADC
transfer function.
SAMPLING
CAPACITOR
COMPARATOR
VIN
SW2
CONVERSION
PHASE
SW1
A
B
AGND
VDD/2
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
02643-021
Figure 20. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7466/AD7467/AD7468 is straight
binary. The designed code transitions occur at successive
integer LSB values; that is, 1 LSB, 2 LSB, and so on. The LSB size
for the devices is as follows:
VDD/4096 for the AD7466
VDD/1024 for the AD7467
VDD/256 for the AD7468
The ideal transfer characteristics for the devices are shown in
111...111
111...110
111...000
011...111
+VDD – 1LSB
0V 1LSB
ANALOG INPUT
ADC
CODE
1LSB = VDD/4096 (AD7466)
1LSB = VDD/1024 (AD7467)
1LSB = VDD/256 (AD7468)
000...010
000...001
000...000
02643-022
Figure 21. AD7466/AD7467/AD7468 Transfer Characteristics
TYPICAL CONNECTION DIAGRAM
Figure 22 shows a typical connection diagram for the devices.
VREF is taken internally from VDD and, therefore, VDD should
be well decoupled. This provides an analog input range of
0 V to VDD.
AD7466
SCLK
SDATA
VIN
GND
0V TO VDD
INPUT
VDD
0.1
μF
10
μF
μC/μP
0.1
μF
1
μF
TANT
REF192
240
μA
680nF
2.5V
5V
SUPPLY
SERIAL
INTERFACE
CS
02643-023
Figure 22. REF192 as Power Supply to AD7466
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