參數(shù)資料
型號(hào): AD7451ARTZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 21/25頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT DIFF 1MSPS SOT23-8
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 1M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 9.25mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8
供應(yīng)商設(shè)備封裝: SOT-23-8
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 1 個(gè)偽差分,單極
其它名稱: AD7451ARTZ-REEL7DKR
AD7441/AD7451
Rev. D | Page 4 of 24
Parameter
Test Conditions/Comments
A Version
B Version
Unit
CONVERSION RATE
Conversion Time
888 ns with an 18 MHz SCLK
16
SCLK cycles
Track-and-Hold Acquisition Time1
Sine wave input
250
ns max
Full-scale step input
290
ns max
Throughput Rate
1
MSPS max
POWER REQUIREMENTS
VDD
2.7/5.25
V min/max
Normal Mode (Static)
SCLK on or off
0.5
mA typ
Normal Mode (Operational)
VDD = 4.75 V to 5.25 V
1.95
mA max
VDD = 2.7 V to 3.6 V
1.45
mA max
Full Power-Down Mode
SCLK on or off
1
μA max
Power Dissipation
Normal Mode (Operational)
VDD = 5 V; 1.55 mW typical for 100 ksps6
9.25
mW max
VDD = 3 V; 0.6 mW typical for 100 ksps6
4
mW max
Full Power-Down
VDD = 5 V; SCLK on or off
5
μW max
VDD = 3 V; SCLK on or off
3
μW max
1 See Terminology section.
2 Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result.
3 A small dc input is applied to VIN– to provide a pseudo ground for VIN+.
4 The AD7451 is functional with a reference input in the range of 100 mV to VDD.
5 Guaranteed by characterization.
6 See the Power vs. Throughput Rate section.
7 Measured with a full-scale dc input.
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