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參數(shù)資料
| 型號： | AD7451ARTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/25頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT DIFF 1MSPS SOT23-8 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 9.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
| 其它名稱： | AD7451ARTZ-REEL7DKR |
AD7441/AD7451
Rev. D | Page 19 of 24
CS
SCLK
SDATA
1
10
16
1
10
16
A
THIS PART IS FULLY POWERED
UP WITH VIN FULLY ACQUIRED
PART BEGINS
TO POWER UP
INVALID DATA
VALID DATA
tPOWER-UP
03
15
3-
0
31
Figure 31. Exiting Power-Down Mode
If CS is brought high before the 10th falling edge of SCLK, the
AD7441/AD7451 again go back into power-down. This avoids
accidental power-up due to glitches on the CS line or an inad-
vertent burst of eight SCLK cycles while CS is low. So although
the device may begin to power up on the falling edge of CS, it
again powers down on the rising edge of CS as long as it occurs
before the 10th SCLK falling edge.
Power-Up Time
The power-up time of the AD7441/AD7451 is typically 1 μs,
which means that with any frequency of SCLK up to 18 MHz,
one dummy cycle is always sufficient to allow the device to
power up. Once the dummy cycle is complete, the ADC is fully
powered up and the input signal is acquired properly. The quiet
time, tQUIET, must still be allowed—from the point at which the
bus goes back into three-state after the dummy conversion to
the next falling edge of CS.
When running at the maximum throughput rate of 1 MSPS,
the AD7441/AD7451 power up and acquire a signal within
±0.5 LSB in one dummy cycle, that is, 1 μs. When powering up
from the power-down mode with a dummy cycle, as in Figure 31,
the track-and-hold, which was in hold mode while the part was
powered down, returns to track mode after the first SCLK edge
the part receives after the falling edge of CS. This is shown as
Point A in
Although at any SCLK frequency one dummy cycle is sufficient
to power up the device and acquire VIN, it does not necessarily
mean that a full dummy cycle of 16 SCLKs must always elapse
to power up the device and acquire VIN fully; 1 μs is sufficient to
power up the device and acquire the input signal.
For example, when a 5 MHz SCLK frequency is applied to the
ADC, the cycle time is 3.2 μs (that is, 1/(5 MHz) × 16). In one
dummy cycle, 3.2 μs, the part is powered up, and VIN is acquired
fully. However, after 1 μs with a five MHz SCLK, only five SCLK
cycles elapse. At this stage, the ADC is fully powered up and the
signal acquired. Therefore, in this case, the CS can be brought
high after the 10th SCLK falling edge and brought low again
after a time, tQUIET, to initiate the conversion.
When power supplies are first applied to the AD7441/AD7451,
the ADC can power up either in power-down mode or normal
mode. For this reason, it is best to allow a dummy cycle to elapse
to ensure that the part is fully powered up before attempting a
valid conversion. Likewise, if the user wants the part to power
up in power-down mode, then the dummy cycle can be used to
ensure the device is in power-down mode by executing a cycle
such as that shown in Figure 30. Once supplies are applied to
the AD7441/AD7451, the power-up time is the same as that
when powering up from power-down mode. It takes approxi-
mately 1 μs to power up fully in normal mode. It is not necessary
to wait 1 μs before executing a dummy cycle to ensure the
desired mode of operation. Instead, the dummy cycle can
occur directly after power is supplied to the ADC. If the first
valid conversion is then performed directly after the dummy
conversion, care must be taken to ensure that adequate
acquisition time has been allowed.
As mentioned earlier, when powering up from the power-down
mode, the part returns to track mode upon the first SCLK edge
applied after the falling edge of CS. However, when the ADC
powers up initially after supplies are applied, the track-and-
hold is already in track mode. This means (assuming one has
the facility to monitor the ADC supply current) that if the ADC
powers up in the desired mode of operation, a dummy cycle is
not required to change mode. Thus, a dummy cycle is also not
required to place the track-and-hold into track.
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