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| 型號： | AD7450ABRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT DIFF IN 1MSPS 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 9.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
| 配用： | EVAL-AD7450CBZ-ND - BOARD EVALUATION FOR AD7450 |
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AD7440/AD7450A
Rev. C | Page 15 of 28
CIRCUIT INFORMATION
The AD7440/AD7450A are 10-bit and 12-bit fast, low power,
single-supply, successive approximation analog-to-digital
converters (ADCs). They can operate with a 5 V or 3 V power
supply and are capable of throughput rates up to 1 MSPS when
supplied with an 18 MHz SCLK. They require an external
reference to be applied to the VREF pin, with the value of the
reference chosen depending on the power supply and what suits
the application.
When they are operated with a 5 V supply, the maximum
reference that can be applied is 3.5 V. When they are operated
with a 3 V supply, the maximum reference that can be applied is
2.2 V (see the Reference section).
The AD7440/AD7450A have an on-chip differential track-and-
hold amplifier, a successive approximation (SAR) ADC, and a
serial interface housed in either an 8-lead SOT-23 or an MSOP
package. The serial clock input accesses data from the part and
provides the clock source for the successive approximation
ADC. The AD7440/AD7450A feature a power-down option for
reduced power consumption between conversions. The power-
down feature is implemented across the standard serial interface
as described in the Modes of Operation section.
CONVERTER OPERATION
The AD7440/AD7450A are successive approximation ADCs
show simplified schematics of the ADC in acquisition and
conversion phase, respectively. The ADC is comprised of
control logic, an SAR, and two capacitive DACs. In Figure 23
(acquisition phase), SW3 is closed, SW1 and SW2 are in
Position A, the comparator is held in a balanced condition,
and the sampling capacitor arrays acquire the differential
signal on the input.
03051-A
-023
VIN+
VIN–
A
B
SW1
SW3
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
CAPACITIVE
DAC
CS
VREF
SW2
B
A
Figure 23. ADC Acquisition Phase
When the ADC starts a conversion (Figure 24), SW3 opens and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistri-
bution DACs are used to add and subtract fixed amounts of
charge from the sampling capacitor arrays to bring the compar-
ator back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC’s output code. The output impedances of the
sources driving the VIN+ and the VIN– pins must be matched;
otherwise, the two inputs have different settling times, resulting
in errors.
03051-A
-024
VIN+
VIN–
A
B
SW1
SW3
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
CAPACITIVE
DAC
CS
VREF
SW2
B
A
Figure 24. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7440/AD7450A is twos
complement. The designed code transitions occur at successive
LSB values (1 LSB, 2 LSBs, and so on). The LSB size of the
AD7450A is 2 × VREF/4096, and the LSB size of the AD7440 is
2 × VREF/1024. The ideal transfer characteristic of the
AD7440/AD7450A is shown in Figure 25.
03051-A
-025
100...000
ANALOG INPUT
(VIN+ – VIN–)
011...111
100...001
100...010
011...110
000...001
111...111
1 LSB
1LSB = 2
×V
REF/4096 AD7450A
1LSB = 2
×V
REF/1024 AD7440
+VREF – 1 LSB
–VREF
0 LSB
000...000
ADC
CODE
Figure 25. AD7440/AD7450A Ideal Transfer Characteristic
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD7450ABRMZ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, 1 MSPS ADCs in an 8-Lead SOT-23 |
| AD7450ABRT-R2 | 功能描述:IC ADC 12BIT W/DIFF INP SOT-23-8 RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD7450ABRT-REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, 1 MSPS 10-Bit and 12-Bit ADCs in an 8-Lead SOT-23 |
| AD7450ABRTZ-REEL7 | 功能描述:IC ADC 12BIT DIFF 1MSPS SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7450ABRTZ-REEL72 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, 1 MSPS ADCs in an 8-Lead SOT-23 |
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