參數(shù)資料
型號： AD7450ABRMZ
廠商： Analog Devices Inc
文件頁數(shù)： 15/29頁
文件大?。?/td> 0K
描述： IC ADC 12BIT DIFF IN 1MSPS 8MSOP
標準包裝： 50
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 9.25mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
輸入數(shù)目和類型： 1 個差分，單極
配用： EVAL-AD7450CBZ-ND - BOARD EVALUATION FOR AD7450
AD7440/AD7450A
Rev. C | Page 21 of 28
Sixteen serial clock cycles are required to perform a conversion
and access data from the AD7440/AD7450A.
SERIAL INTERFACE
CS going low
provides the first leading zero to be read in by the DSP or
microcontroller. The remaining data is then clocked out on the
subsequent SCLK falling edges beginning with the second
leading zero. Thus, the first falling clock edge on the serial clock
provides the second leading zero. The final bit in the data
transfer is valid on the 16th falling edge, having been clocked
out on the previous (15th) falling edge. Once the conversion is
complete and the data has been accessed after the 16 clock
cycles, it is important to ensure that before the next conversion
is initiated, enough time is left to meet the acquisition and
quiet time specifications (see Timing Examples 1 and 2). To
achieve 1 MSPS with an 18 MHz clock for V
Figure 2 and Figure 3 show detailed timing diagrams for the
serial interface of the AD7450A and the AD7440, respectively.
The serial clock provides the conversion clock and also controls
the transfer of data from the devices during conversion. CS
initiates the conversion process and frames the data transfer.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state. The analog input is sampled
and the conversion is initiated at this point. The conversion
requires 16 SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track-and-hold
goes back into track on the next SCLK rising edge, as shown at
Point B in
DD
= 3 V and 5 V, an
18-clock burst performs the conversion and leaves enough time
before the next conversion for the acquisition and quiet time.
Figure 2 and Figure 3. On the 16th SCLK falling
edge, the SDATA line goes back into three-state. If the rising
edge of CS occurs before 16 SCLKs have elapsed, the conversion
terminates and the SDATA line goes back into three-state.
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge; that is, the first rising edge of
SCLK after the
The conversion result from the AD7440/AD7450A is provided
on the SDATA output as a serial data stream. The bits are
clocked out on the falling edge of the SCLK input. The data
stream of the AD7450A consists of four leading zeros followed
by 12 bits of conversion data provided MSB first; the data
stream of the AD7440 consists of four leading zeros, followed
by the 10 bits of conversion data followed by two trailing zeros,
which is also provided MSB first. In both cases, the output
coding is twos complement.
CS falling edge would have the leading zero
provided and the 15th SCLK edge would have DB0 provided.
03051-A
-040
t2
t8
t6
t5
tCONVERT
CS
SCLK
12
3
4
5
13
14
15
16
12.5(1/FSCLK)
tACQUISITION
1/THROUGHPUT
tQUIET
10ns
B
C
Figure 40. Serial Interface Timing Example
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