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參數(shù)資料
| 型號(hào)： | AD7392 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Parallel Input Micropower 10- and 12-Bit DACs(并行輸入微功耗12位D/A轉(zhuǎn)換器) |
| 中文描述： | 并行輸入微10 -和12位DAC（并行輸入微功耗12位的D / A轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 331K |
| 代理商： | AD7392 |
AD7392/AD7393
–7–
REV. 0
TIME – 100μs/DIV
100
50
0
2
0
1
0
10
0%
100
90
500mV
2V
100μs
5V
AD7392
V
DD
= +5V
V
= +2.5V
CODE = FFF
H
R
L
= 1M
TO GND
T
A
= 25
8
C
IDD (μA)
V
OUT
(V)
SHDN
Figure 23. Shutdown Recovery Time
TEMPERATURE –
°
C
S
1000
10
–55 –35
125
–15
65
85
105
5
25
45
100
V
DD
= 5.5V
V
REF
= 2.5V
SHDN
= 0V
AD7392
Figure 24. Shutdown Current vs. Temperature
Table I. Control Logic Truth Table
CS
RS
DAC Register Function
H
L
↑
X
H
H
H
H
L
↑
Latched
Transparent
Latched with New Data
Loaded with All Zeros
Latched all Zeros
NOTE
↑
Positive logic transition; X Don’t Care.
OPERATION
The AD7392 and AD7393 comprise a set of pin compatible,
12-bit/10-bit digital-to-analog converters. These single-supply
operation devices consume less than 100 microamps of current
while operating from power supplies in the +2.7 V to +5.5 V
range making them ideal for battery operated applications. They
contain a voltage-switched, 12-bit/10-bit, laser-trimmed digital-
to-analog converter, rail-to-rail output op amps, and a parallel-
input DAC register. The external reference input has constant
input resistance independent of the digital code setting of the
DAC. In addition, the reference input can be tied to the same
supply voltage as V
DD
, resulting in a maximum output voltage
span of 0 to V
DD
. The parallel data interface consists of 12 data
bits, DB0–DB11, for the AD7392; 10 data bits, DB0–DB9, for
the AD7393; and a
CS
write strobe. A
RS
pin is available to
reset the DAC register to zero scale. This function is useful for
power-on reset or system failure recovery to a known state.
Additional power savings are accomplished by activating the
SHDN
pin, resulting in a 1.5
μ
A maximum consumption sleep
mode. As long as the supply voltage remains, data will be
retained in the DAC register to reset the DAC output when the
part is taken out of shutdown (
SHDN
= 1).
D/A CONVERTER SECTION
The voltage switched R-2R DAC generates an output voltage
dependent on the external reference voltage connected to the
REF pin according to the following equation:
V
OUT
=
V
REF
×
D
2
N
Equation 1
where
D
is the decimal data word loaded into the DAC register,
and
N
is the number of bits of DAC resolution. In the case of
the 10-bit AD7393 using a 2.5 V reference, Equation 1 simpli-
fies to:
V
OUT
=
2.5
×
1024
Using Equation 2, the nominal midscale voltage at V
OUT
is 1.25 V
for
D
= 512; full-scale voltage is 2.497 volts. The LSB step size is
= 2.5
×
1/1024 = 0.0024 volts.
For the 12-bit AD7392 operating from a 5.0 V reference
Equation 1 becomes:
D
Equation 2
V
OUT
=
V
REF
×
D
2
N
Equation 3
Using Equation 3, the AD7392 provides a nominal midscale
voltage of 2.50 V for D = 2048, and a full-scale output of 4.998
volts. The LSB step size is = 5.0
×
1/4096 = 0.0012 volts.
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