參數(shù)資料
型號： AD7366BRUZ-5
廠商： Analog Devices Inc
文件頁數(shù)： 18/28頁
文件大?。?/td> 0K
描述： IC ADC 12BIT DUAL 500KSPS 24-TSS
設(shè)計資源： Driving the AD7366/7 Bipolar SAR ADC in Low-Distortion DC-Coupled Appls (CN0042)
標(biāo)準(zhǔn)包裝： 62
系列： iCMOS®
位數(shù)： 12
采樣率（每秒）： 500k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 88.8mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
輸入數(shù)目和類型： 4 個單端，單極；4 個單端，雙極
配用： EVAL-AD7366CBZ-ND - BOARD EVALUATION FOR AD7366
AD7366-5/AD7367-5
Rev. A | Page 25 of 28
DEVICE B
(SECONDARY)
AD7366-5/AD7367-5 TO ADSP-BF53x
The ADSP-BF53x family of DSPs interfaces directly to the
AD7366-5/AD7367-5 with no glue logic required. The availability
of secondary receive registers on the serial ports of the Blackfin
DSPs means that only one serial port is necessary to read from
both DOUTA and DOUTB pins simultaneously. Figure 30 shows
DOUTA and DOUTB of the AD7366-5/AD7367-5 connected to
Serial Port 0 of the ADSP-BF53x. The SPORT0 Receive
Configuration 1 register and SPORT0 Receive Configuration 2
register should be set up as outlined in Table 13 and Table 14.
SERIAL
DEVICE A
(PRIMARY)
SERIAL
AD7366-5/
AD7367-5*
DOUTA
CS
SCLK
ADSP-BF53x*
DR0PRI
PFn
RFS0
V
*ADDITIONAL PINS OMITTED FOR CLARITY.
DRIVE
VDD
CNVST
RCLKO
RXINPUTS
BUSY
DR0SEC
DOUTB
SPORT0
0
68
42
-0
32
Figure 30. Interfacing the AD7366-5/AD7367-5 to the ADSP-BF53x
Table 13. SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1) Setup
Setting
Description
RCKFE = 1
Sample data with falling edge of RSCLK.
LRFS = 1
Active low frame signal.
RFSR = 1
Frame every word.
IRFS = 1
Internal RFS used.
RLSBIT = 0
Receive MSB first.
RDTYPE = 00
Zero fill.
IRCLK = 1
Internal receive clock.
RSPEN = 1
Receive enabled.
SLEN = 1111
16-bit data-word (or can be set to 1101 for
14-bit data-word).
TFSR = RFSR = 1
Table 14. SPORT0 Receive Configuration 2 Register
(SPORT0_RCR2) Setup
Setting
Description
RXSE = 1
Secondary side enabled.
SLEN = 1111
16-bit data-word (or can be set to 1101 for
14-bit data-word).
AD7366-5/AD7367-5 TO TMS320VC5506
The serial interface on the TMS320VC5506 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7366-5/AD7367-5. The CS input allows easy interfacing
between the TMS320VC5506 and the AD7366-5/AD7367-5
with no glue logic required. The serial ports of the TMS320VC5506
are set up to operate in burst mode with internal CLKX0 (Tx
serial clock on Serial Port 0) and FSX0 (Tx frame sync from
Serial Port 0). The connection diagram is shown in
.
The serial port control registers (SPC) must be setup as shown
in
.
FSR1
FSR0
AD7366-5/
AD7367-5*
SCLK
TMS320VC5506*
*ADDITIONAL PINS OMITTED FOR CLARITY.
CLKX0
DR1
CLKR1
CLKX1
DOUTB
DOUTA
VDRIVE
VDD
CS
FSX0
DR0
CLKR0
INTn
XF
CNVST
BUSY
06
84
2-
0
3
Figure 31. Interfacing the AD7366-5/AD7367-5 to the TMS320VC5506
Table 15. Serial Port Control Register Setup
SPC
FO
FSM
MCM
TXM
SPC0
0
1
SPC1
0
1
0
The VDRIVE pin of the AD7366-5/AD7367-5 takes the same
supply voltage as that of the TMS320VC5506. This allows the
ADC to operate at a higher voltage than its serial interface and,
therefore, the TMS320VC5506, if necessary.
As with the previous interfaces, conversion can be initiated
from the TMS320VC5506 or from an external source, and the
processor is interrupted when the conversion sequence is
complete.
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