參數(shù)資料
型號: AD7366BRUZ-5
廠商: Analog Devices Inc
文件頁數(shù): 17/28頁
文件大?。?/td> 0K
描述: IC ADC 12BIT DUAL 500KSPS 24-TSS
設計資源: Driving the AD7366/7 Bipolar SAR ADC in Low-Distortion DC-Coupled Appls (CN0042)
標準包裝: 62
系列: iCMOS®
位數(shù): 12
采樣率(每秒): 500k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 88.8mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 24-TSSOP
包裝: 管件
輸入數(shù)目和類型: 4 個單端,單極;4 個單端,雙極
配用: EVAL-AD7366CBZ-ND - BOARD EVALUATION FOR AD7366
AD7366-5/AD7367-5
Rev. A | Page 24 of 28
MICROPROCESSOR INTERFACING
The serial interface on the AD7366-5/AD7367-5 allows the
parts to be directly connected to a range of different micro-
processors. This section explains how to interface the AD7366-5/
AD7367-5 with some more common microcontrollers and DSP
serial interface protocols.
Table 11. SPORT0 Control Register Setup
Setting
Description
TFSW = RFSW = 1
Alternate framing.
INVRFS = INVTFS = 1
Active low frame signal.
DTYPE = 00
Right justify data.
SLEN = 1111
16-bit data-word (or can be set to 1101
for 14-bit data-word).
ISCLK = 1
Internal serial clock.
TFSR = RFSR = 1
Frame every word.
IRFS = 0
ITFS = 1
AD7366-5/AD7367-5 TO ADSP-218x
The ADSP-218x family of DSPs interfaces directly to the
AD7366-5/AD7367-5 with no glue logic required. The VDRIVE
pin of the AD7366-5/AD7367-5 takes the same supply voltage
as that of the ADSP-218x. This allows the ADC to operate at a
higher supply voltage than its serial interface and therefore, the
ADSP-218x, if necessary. The connection diagram in Figure 29
shows both DOUTA and DOUTB of the AD7366-5/AD7367-5
connected to both serial ports of the ADSP-218x. The SPORT0
and SPORT1 control registers should be set up as shown in
Table 12. SPORT1 Control Register Setup
Setting
Description
TFSW = RFSW = 1
Alternate framing.
INVRFS = INVTFS = 1
Active low frame signal.
DTYPE = 00
Right justify data.
SLEN = 1111
16-bit data-word (or can be set to 1101
for 14-bit data-word).
ISCLK = 0
External serial clock.
TFSR = RFSR = 1
Frame every word.
IRFS = 0
ITFS = 1
AD7366-5/
AD7367-5*
SCLK
CS
ADSP-218x*
SCLK0
DR0
RFS0
TFS0
DOUTA
VDRIVE
*ADDITIONAL PINS OMITTED FOR CLARITY.
VDD
DOUTBDR1
RFS1
SCLK1
IRQn
BUSY
CNVST
FLn
The ADSP-218x has the TFS0 and RFS0 of the SPORT0 and the
RFS1 of SPORT1 tied together. TFS0 is set as an output, and both
RFS0 and RFS1 are set as inputs. The DSP operates in alternate
framing mode, and the SPORT control registers are set up as
described in Table 11 and Table 12. The frame synchronization
signal generated on the TFS0 is tied to CS.
The AD7366-5/AD7367-5 BUSY line provides an interrupt to
the ADSP-218x when the conversion is complete. The conversion
results can then be read from the AD7366-5/AD7367-5 using a
read operation. When an interrupt is received on IRQn from the
BUSY signal, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and, therefore, the
reading of data.
06
84
2-
0
31
Figure 29. Interfacing the AD7366-5/AD7367-5 to the ADSP-218x
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