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參數(shù)資料
| 型號： | AD73511 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low-Power CMOS Analog Front End with Flash based DSP Microcomputer(帶閃速DSP微計算機(jī)的單模擬前端) |
| 中文描述： | 低功耗CMOS模擬前端與閃存的DSP微機(jī)（帶閃速DSP的微計算機(jī)的單模擬前端） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 77K |
| 代理商： | AD73511 |
AD73511
–9–
REV. PrA 08/99
Prelimnary Technical Data
Analog Ground/Substrate Connection for Codec 1.
Analog Power Supply Connection for Codec 1.
(Input) Processor Reset Input
(Input) Bus Request Input
(Output) Bus Grant Output
(Output) Bus Grant Hung Output
(Output) Data Memory Select Output
(Output) Program Memory Select Output
(Output) Memory Select Output
(Output) Byte Memory Select Output
(Output) Combined Memory Select Output
(Output) Memory Read Enable Output
(Output) Memory Write Enable Output
(Input) Edge- or Level-Sensitive Interrupt
(Input/Output) Request.
1
Programmable I/O Pin
(Input) Level-Sensitive Interrupt Requests
1
(Input/Output) Programmable I/O Pin
(Input) Level-Sensitive Interrupt Requests
1
(Input/Output) Programmable I/O Pin
(Input) Edge-Sensitive Interrupt Requests
1
(Input/Output) Programmable I/O Pin
(Input) Mode Select Input—Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
(Input) Mode Select Input—Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
(Input) Mode Select Input—Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
TECHNCAL
original values (before SE was brought low), however the timing counters and other internal registers are at their
reset values.
PIN FUNC T ION DE SC RIPT ION
Mnemonic
Function
VINP
VINN
REFOUT
REFC AP
Analog Input to the positive terminal of the input Channel.
Analog Input to the negative terminal of the input Channel.
Buffered Reference Output, which has a nominal value of 1.2 V.
A Bypass Capacitor to AGND2 of 0.1 μF is required for the on-chip reference. T he capacitor should be fixed to
this pin.
Analog Power Supply Connection for Codec 2.
Analog Ground/Substrate Connection for Codec 2.
Digital Ground/Substrate Connection.
Digital Power Supply Connection.
Active Low Reset Signal. T his input resets the entire chip, resetting the control registers and clearing the digital
circuitry.
Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock data or
control information to and from the serial port (SPORT ). T he frequency of SCLK is equal to the frequency of
the master clock (MCLK ) divided by an integer number—this integer number being the product of the external
master clock rate divider and the serial clock rate divider.
Master Clock Input. MCLK is driven from an external clock signal.
Serial Data Output of the Codec. Both data and control information may be output on this pin and is clocked on
the positive edge of SCLK . SDO is in three-state when no information is being transmitted and when SE is low.
Framing Signal Output for SDO Serial T ransfers. T he frame sync is one-bit wide and it is active one SCLK
period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK .
SDOFS is in three-state when SE is low.
Framing Signal Input for SDI Serial T ransfers. T he frame sync is one-bit wide and it is valid one SCLK period
before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored
when SE is low.
Serial Data Input of the Codec. Both data and control information may be input on this pin and are clocked on
the negative edge of SCLK . SDI is ignored when SE is low.
SPORT Enable. Asynchronous input enable pin for the SPORT . When SE is set low by the DSP, the output pins
of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to
decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are at their
AVDD2
AGND2
DGND
DVDD
ARESET
SC L K
MC L K
SD O
SDOFS
SDIFS
SDI
SE
AGND1
AVDD1
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2
/
PF7
IRQL0
/
PF6
IRQL1
/
PF5
IRQE
/
PF4
Mode D/
PF3
Mode C/
PF2
Mode B/
PF1
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