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| 型號(hào)： | AD73511 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low-Power CMOS Analog Front End with Flash based DSP Microcomputer(帶閃速DSP微計(jì)算機(jī)的單模擬前端) |
| 中文描述： | 低功耗CMOS模擬前端與閃存的DSP微機(jī)（帶閃速DSP的微計(jì)算機(jī)的單模擬前端） |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大小： | 77K |
| 代理商： | AD73511 |
AD73511
–2–
REV. PrA 08/99
Prelimnary Technical Data
PRELMNARY
DATA
Figure 1 is an overall block diagram of the AD73511. T he
processor section contains three independent computational
units: the ALU, the multiplier/accumulator (MAC) and the
shifter. T he computational units process 16-bit data directly
and have provisions to support multiprecision computations.
T he ALU performs a standard set of arithmetic and logic
operations; division primitives are also supported. T he MAC
performs single-cycle multiply, multiply/add and multiply/
subtract operations with
40 bits of accumulation. T he shifter performs logical and
arithmetic shifts, normalization, denormalization and derive
exponent operations.
T he internal result (R) bus connects the computational units
so that the output of any unit may be the input of any unit on
the next cycle.
TECHNCAL
master RESET signal. T he two serial ports provide a complete
synchronous serial interface with optional companding in
hardware and a wide variety of framed or frameless data transmit
and receive modes of operation.
Each port can generate an internal programmable serial clock
or accept an external serial clock.
T he AD73511 provides up to 13 general-purpose flag pins.
T he data input and output pins on SPORT 1 can be
alternatively configured as an input flag and an output flag. In
addition, there are eight flags that are programmable as inputs
or outputs and three flags that are always outputs.
A programmable interval timer generates periodic interrupts.
A 16-bit count register (T COUNT ) is decremented every
n
processor cycle, where
n
is a scaling value stored in an 8-bit
register (T SCALE). When the value of the count register
reaches zero, an interrupt is generated and the count register
is reloaded from a 16-bit period register (T PERIOD).
AR C HIT E C T UR E OVE R VIE W
T he AD73511 instruction set provides flexible data moves
and multifunction (one or two data moves with a
computation) instructions. Every instruction can be executed
in a single processor cycle. T he AD73511 assembly language
uses an algebraic syntax for ease of coding and readability. A
comprehensive set of development tools supports program
development.
ADC
DAC
EXTERNAL
BUS
BYTE DMA
CONTROLLER
EXTERNAL
DATA
BUS
FULMODE
SERIAL PORTS
SPORT 0
SHIFTER
MAC
ALU
ARITHMETIC UNITS
MEMORY
PROGRI/O
AND
FLAGS
TIMER
ADSP-2100 BASE
ARCHITECTURE
POWER-DOWN
CONTROL
PROGRAM
SEQUENCER
DAG 2
DATA
GADDRESS
DAG 1
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
16K DM
(OP8K)
16K PM
(OP8K)
SPORT 1
SERIAL PORT
SPORT 2
REF
ANALOG FRONT END
SECTION
FLASH
MEMORY
64 KBYTES
Figure 1. Functional Block Diagram
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. T he sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the AD73511 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
T wo data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one
of four possible modify registers. A length value may be
associated with each pointer to implement automatic modulo
addressing for
circular buffers.
T he two address buses (PMA and DMA) share a single
external address bus, allowing memory to be expanded off-
chip, and the two data buses (PMD and DMD) share a single
external data bus. Byte memory space and I/O memory space
also share the external buses.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). T he BDMA port is
bidirectional and can directly address up to four megabytes of
external RAM or ROM for off-chip storage of program
overlays or data tables.
T he AD73511 can respond to eleven interrupts. T here can be
up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORT s), the Byte
DMA port and the power-down circuitry. T here is also a
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