- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375236 > AD734 (Analog Devices, Inc.) 10 MHz, 4-Quadrant Multiplier/Divider(10MHz,四象限乘法器/除法器) PDF資料下載
參數(shù)資料
| 型號： | AD734 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10 MHz, 4-Quadrant Multiplier/Divider(10MHz,四象限乘法器/除法器) |
| 中文描述： | 10兆赫，四象限乘法器/除法器（10MHz的，四象限乘法器/除法器） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 283K |
| 代理商： | AD734 |
AD734
REV. B
–9–
A PRE CISION AGC LOOP
T he variable denominator of the AD734 and its high gain-
bandwidth product make it an excellent choice for precise
automatic gain control (AGC) applications. Figure 13 shows a
suggested method. T he input signal, E
IN
, which may have a
peak amplitude of from 10 mV to 10 V at any frequency from
100 Hz to 10 MHz, is applied to the X input, and a fixed posi-
tive voltage E
C
to the Y input. Op amp A2 and capacitor C2
form an integrator having a current summing node at its invert-
ing input. (T he AD712 dual op amp is a suitable choice for this
application.) In the absence of an input, the current in D2 and
R2 causes the integrator output to ramp negative, clamped by
diode D3, which is included to reduce the time required for the
loop to establish a stable, calibrated, output level once the
circuit has received an input signal. With no input to the
denominator (U0 and U2), the gain of the AD734 is very high
(about 70 dB), and thus even a small input causes a substantial
output.
E
OUT
D3
1N914
R2
1M
R1
1M
C1
1μF
E
IN
R3
1M
AD734
OP AMP = AD712 DUAL
1
2
3
4
5
6
7
10
8
9
11
13
12
14
W
ER
VN
VP
DD
Z1
Z2
X1
X2
U1
U2
U0
Y1
Y2
L
0.1μF
0.1μF
+15V
–15V
A1
NC
C2
1μF
A2
D2
1N914
+1V TO
+10V
E
C
D1
1N914
C1
1μF
L
Figure 13. Precision AGC Loop
Diode D1 and C1 form a peak detector, which rectifies the out-
put and causes the integrator to ramp positive. When the cur-
rent in R1 balances the current in R2, the integrator output
holds the denominator output at a constant value. T his occurs
when there is sufficient gain to raise the amplitude of E
IN
to that
required to establish an output amplitude of E
C
over the range
of +1 V to +10 V. T he X input of the AD734, which has finite
offset voltage, could be troublesome at the output at high gains.
T he output offset is reduced to that of the X input (one or two
millivolts) by the offset loop comprising R3, C3, and buffer A1.
T he low pass corner frequency of 0.16 Hz is transformed to a
high-pass corner that is multiplied by the gain (for example,
160 Hz at a gain of 1000).
In applications not requiring operation down to low frequencies,
amplifier A1 can he eliminated, but the AD734’s input
resistance of 50 k
between X 1 and X 2 will reduce the time
constant and increase the input offset. Using a non-polar 20
μ
F
tantalum capacitor for C1 will result in the same unity-gain
high-pass corner; in this case, the offset gain increases to 20, still
very acceptable.
Figure 14 shows the error in the output for sinusoidal inputs at
100 Hz, 100 kHz, and 1 MHz, with E
C
set to +10 V. T he out-
put error for any frequency between 300 Hz and 300 kHz is
similar to that for 100 kHz. At low signal frequencies and low
input amplitudes, the dynamics of the control loop determine
the gain error and distortion; at high frequencies, the 200 MHz
gain-bandwidth product of the AD734 limit the available gain.
T he output amplitude tracks E
C
over the range +1 V to slightly
more than +10 V.
+2
+1
0
–1
–2
10mV
E
–
d
100kH
Z
100H
Z
1MH
Z
100mV
INPUT AMPLITUDE – Volts
1V
10V
Figure 14. AGC Amplifier Output Error vs. Input Voltage
WIDE BAND RMS-DC CONVE RT E R
USING U INT E RFACE
T he AD734 is well suited to such applications as implicit RMS-
DC conversion, where the AD734 implements the function
[
V
RMS
V
RMS
=
avg V
IN
2
]
(13)
using its direct divide mode. Figure 15 shows the circuit.
L
1/2
AD708
V
IN
2
V
O
=
V
O
R1
3.32k
V
IN
1
2
3
4
5
6
7
10
8
9
11
13
12
14
W
ER
VN
VP
DD
Z1
Z2
X1
X2
U1
U2
U0
Y1
Y2
AD734
0.1μF
0.1μF
+15V
–15V
U2a
C1
47μF
U1
L
L
L
C2
1μF
L
L
L
1/2
AD708
U2b
Figure 15. A 2-Chip, Wideband RMS-DC Converter
In this application, the AD734 and an AD708 dual op amp
serve as a 2-chip RMS-DC converter with a 10 MHz bandwidth.
Figure 16 shows the circuit’s performance for square-, sine-,
and triangle-wave inputs. T he circuit accepts signals as high as
10 V p-p with a crest factor of 1 or 1 V p-p with a crest factor of
10. T he circuit’s response is flat to 10 MHz with an input of
10 V, flat to almost 5 MHz for an input of 1 V, and to almost
1 MHz for inputs of 100 mV. For accurate measurements of
input levels below 100 mV, the AD734’s output offset (Z inter-
face) voltage, which contributes a dc error, must be trimmed out.
In Figure 15’s circuit, the AD734 squares the input signal, and
its output (V
IN2
) is averaged by a low-pass filter that consists of
R1 and C1 and has a corner frequency of 1 Hz. Because of the
implicit feedback loop, this value is both the output value, V
RMS
,
and the denominator in Equation (13). U2a and U2b, an
AD708 dual dc precision op amp, serve as unity-gain buffers,
supplying both the output voltage and driving the U interface.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD73511 | Low-Power CMOS Analog Front End with Flash based DSP Microcomputer(帶閃速DSP微計(jì)算機(jī)的單模擬前端) |
| AD7392 | Parallel Input Micropower 10- and 12-Bit DACs(并行輸入微功耗12位D/A轉(zhuǎn)換器) |
| AD7395 | +3 V, Dual, Serial Input 12-/10-Bit DACs |
| AD7395AN | +3 V, Dual, Serial Input 12-/10-Bit DACs |
| AD7395AR | +3 V, Dual, Serial Input 12-/10-Bit DACs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD73411 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low-Power Analog Front End with DSP Microcomputer |
| AD73411BB-40 | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 119-Pin BGA 制造商:Rochester Electronics LLC 功能描述:ANALOG FRONT-END PROCESSOR +DSP I.C. - Bulk |
| AD73411BB-80 | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 119-Pin BGA 制造商:Rochester Electronics LLC 功能描述:ANALOG FRONT-END PROCESSOR +DSP I.C. - Bulk |
| AD7341JN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD7341JP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。