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參數(shù)資料
| 型號： | AD734 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10 MHz, 4-Quadrant Multiplier/Divider(10MHz,四象限乘法器/除法器) |
| 中文描述： | 10兆赫，四象限乘法器/除法器（10MHz的，四象限乘法器/除法器） |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 283K |
| 代理商： | AD734 |
AD734
REV. B
–4–
ac-coupled and the other is grounded, the residual offset voltage
is typically less than 5 mV, which corresponds to a bias current
of only 100 nA. T his low bias current ensures that mismatches
in the sources resistances at a pair of inputs does not cause an
offset error. T hese currents remain low over the full temperature
range and supply voltages.
T he common-mode range of the X , Y and Z inputs does not
fully extend to the supply rails. Nevertheless, it is often possible
to operate the AD734 with one terminal of an input pair con-
nected to either the positive or negative supply, unlike previous
multipliers. T he common-mode resistance is several megohms.
T he full-scale output of
±
10 V can be delivered to a load resis-
tance of 1 k
(although the specifications apply to the standard
multiplier load condition of 2 k
). T he output amplifier is
stable driving capacitive loads of at least 100 pF, when a slight
increase in bandwidth results from the peaking caused by this
capacitance. T he 450 V/
μ
s slew rate of the AD734’s output am-
plifier ensures that the bandwidth of 10 MHz can be maintained
up to the full output of 20 V pk-pk. Operation at reduced supply
voltages is possible, down to
±
8 V, with reduced signal levels.
Available T ransfer Functions
T he uncommitted (open-loop) transfer function of the AD734 is
W
=
A
O
X
1
X
2
(
)
Y
1
Y
2
U
(
)
Z
1
Z
2
(
)
,
(1)
where A
O
is the open-loop gain of the output op-amp, typically
72 dB. When a negative feedback path is provided, the circuit
will force the quantity inside the brackets essentially to zero,
resulting in the equation
(X
1
– X
2
)(Y
1
– Y
2
) = U (Z
1
– Z
2
)
T his is the most useful generalized transfer function for the
AD734; it expresses a balance between the product X Y and the
product UZ. T he absence of the output, W, in this equation
only reflects the fact that we have not yet specified which of the
inputs is to be connected to the op amp output.
Most of the functions of the AD734 (including division, unlike
the AD534 in this respect) are realized with Z
1
connected to W.
So, substituting W in place of Z
1
in the above equation results in
an output.
(
U
(2)
W
=
X
1
X
2
)
Y
1
Y
2
(
)
+
Z
2
.
(3)
T he free input Z2 can be used to sum another signal to the
output; in the absence of a product signal, W simply follows the
voltage at Z2 with the full 10 MHz bandwidth. When not
needed for summation, Z2 should be connected to the ground
associated with the load circuit. We can show the allowable
polarities in the following shorthand form:
(
+
U
(
±
W
(
)
=
±
X
)
±
Y
(
)
)
+ ±
Z
.
(4)
In the recommended direct divider mode, the Y input is set to a
fixed voltage (typically 10 V) and U is varied directly; it may
have any value from 10 mV to 10 V. T he magnitude of the ratio
X /U cannot exceed 1.25; for example, the peak X -input for U
= 1 V is
±
1.25 V. Above this level, clipping occurs at the
positive and negative extremities of the X -input. Alternatively,
Ru
DENOMINATOR
CONTROL
DD
ER
∑
XY/U – Z
∞
XZ
U
HIGH-ACCURACY
TRANSLINER
MULTIPLIER CORE
AD734
X1
X2
U0
U1
U2
Y1
Y2
W
Z1
Z2
U
X = X
1
– X
2
Y = Y
1
– Y
2
Z = Z
1
– Z
2
WIF
ZIF
A
O
XIF
YIF
Figure 1. AD734 Block Diagram
FUNCT IONAL DE SCRIPT ION
Figure 1 is a simplified block diagram of the AD734. Operation
is similar to that of the industry-standard AD534 and in many
applications these parts are pin-compatible. T he main functional
difference is the provision for direct control of the denominator
voltage, U, explained fully on the following page. Internal sig-
nals are actually in the form of currents, but the function of the
AD734 can be understood using voltages throughout, as shown
in this figure. Pins are named using upper-case characters (such
as X 1, Z2) while the
voltages
on these pins are denoted by sub-
scripted variables (for example, X
1
, Z
2
).
T he AD734’s differential X , Y and Z inputs are handled by
wideband interfaces that have low offset, low bias current and
low distortion. T he AD734 responds to the difference signals
X = X
1
– X
2
, Y = Y
1
– Y
2
and Z = Z
1
– Z
2
, and rejects
common-mode voltages on these inputs. T he X , Y and Z
interfaces provide a nominal full-scale (FS) voltage of
±
10 V,
but, due to the special design of the input stages, the linear
range of the differential input can be as large as
±
17 V. Also
unlike previous designs, the response on these inputs is not
clipped abruptly above
±
15 V, but drops to a slope of one half.
T he bipolar input signals X and Y are multiplied in a translinear
core of novel design to generate the product X Y/U. T he denom-
inator voltage, U, is internally set to an accurate, temperature-
stable value of 10 V, derived from a buried-Zener reference. An
uncalibrated fraction of the denominator voltage U appears
between the voltage reference pin (ER) and the negative supply
pin (VN), for use in certain applications where a temperature-
compensated voltage reference is desirable. T he internal denom-
inator, U, can be disabled, by connecting the denominator
disable Pin 13 (DD) to the positive supply pin (VP); the denom-
inator can then be replaced by a fixed or variable external volt-
age ranging from 10 mV to more than 10 V.
T he high-gain output op-amp nulls the difference between
X Y/U and an additional signal Z, to generate the final output
W. T he actual transfer function can take on several forms, de-
pending on the connections used. T he AD734 can perform all
of the functions supported by the AD534, and new functions
using the direct-division mode provided by the U-interface.
Each input pair (X 1 and X 2, Y1 and Y2, Z1 and Z2) has a
differential input resistance of 50 k
; this is formed by “real”
resistors (not a small-signal approximation) and is subject to a
tolerance of
±
20%. T he common-mode input resistance is
several megohms and the parasitic capacitance is about 2 pF.
T he bias currents associated with these inputs are nulled by
laser-trimming, such that when one input of a pair is optionally
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