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參數(shù)資料
| 型號： | AD734 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10 MHz, 4-Quadrant Multiplier/Divider(10MHz,四象限乘法器/除法器) |
| 中文描述： | 10兆赫，四象限乘法器/除法器（10MHz的，四象限乘法器/除法器） |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 283K |
| 代理商： | AD734 |
AD734
REV. B
–7–
Current Output
It may occasionally be desirable to convert the output voltage to
a current. In correlation applications, for example, multiplica-
tion is followed by integration; if the output is in the form of a
current, a simple grounded capacitor can perform this function.
Figure 6 shows how this can be achieved. T he op amp forces
the voltage across Z1 and Z2, and thus across the resistor R
S
, to
be the product X Y/U. Note that the input resistance of the
Z interface is in shunt with R
S
, which must be calculated
accordingly.
T he smallest FS current is simply
±
10 V/50 k
, or
±
200
μ
A,
with a tolerance of about 20%. T o guarantee a 1% conversion
tolerance without adjustment, R
S
must be less than 2.5 k
. T he
maximum full scale output current should be limited to about
±
10 mA (thus, R
S
= 1 k
). T his concept can be applied to all
connection modes, with the appropriate choice of terminals.
Squaring and Frequency-Doubling
Squaring of an input signal, E, is achieved simply by connecting
the X and Y inputs in parallel; the phasing can be chosen to
produce an output of E
2
/U or –E
2
/U as desired. T he input may
have either polarity, but the basic output will either always be
positive or negative; as for multiplication, the Z2 input may be
used to add a further signal to the output.
When the input is a sinewave, a squarer behaves as a frequency-
doubler, since
(Esinwt)
2
= E
2
(1 – cos2wt)/2
Equation (8) shows a dc term at the output which will vary
strongly with the amplitude of the input, E. T his dc term can be
avoided using the connection shown in Figure 7, where an
RC-network is used to generate two signals whose product has
no dc term. T he output is
(8)
W
=
4
E
2
sin
wt
+π
4
E
2
sin
wt
π
4
1
10
V
(9)
for
w
= 1/CR1, which is just
W
= E
2
(
cos
2
wt
)/( 10 V)
which has no dc component. T o restore the output to
±
10 V
when E = 10 V, a feedback attenuator with an approximate ratio
of 4 is used between W and Z1; this technique can be used
wherever it is desired to achieve a higher overall gain in the
transfer function.
In fact, the values of R3 and R4 include additional compensa-
tion for the effects of the 50 k
input resistance of all three
interfaces; R2 is included for a similar reason. T hese resistor
values should not be altered without careful calculation of the
consequences; with the values shown, the center frequency f
O
is
100 kHz for C = 1 nF. T he amplitude of the output is only a
weak function of frequency: the output amplitude will be 0.5%
too low at f = 0.9f
0
and f = 1.1f0. T he cross-connection is
simply to produce the cosine output with the sign shown in
Equation (10); however, the sign in this case will rarely be
important.
(10)
R2
1.6k
R1
1.6k
C
Esin
ω
t
R3
13k
R4
4.32k
E cos2
ω
t
/10V
1
2
3
4
5
6
7
10
8
9
11
13
12
14
W
ER
VN
VP
DD
Z1
Z2
X1
X2
U1
U2
U0
Y1
Y2
AD734
NC
NC
0.1μF
0.1μF
+15V
–15V
L
L
L
Figure 7. Frequency Doubler
OPE RAT ION AS A DIVIDE R
T he AD734 supports two methods for performing analog
division. T he first is based on the use of a multiplier in a feed-
back loop. T his is the standard mode recommended for multi-
pliers having a fixed scaling voltage, such as the AD534, and
will be described in this Section. T he second uses the AD734’s
unique capability for externally varying the scaling (denominator)
voltage directly, and will be described in the next section.
Feedback Divider Connections
Figure 8 shows the connections for the standard (AD534)
divider mode. Feedback from the output, W, is now taken to the
Y2 (inverting) input, which, provided that the X -input is posi-
tive, establishes a negative feedback path. Y1 should normally
be connected to the ground associated with the load circuit, but
may optionally be used to sum a further signal to the output. If
desired, the polarity of the Y-input connections can be reversed,
with W connected to Y1 and Y2 used as the optional sum-
mation input. In this case, either the polarity of the X -input
connections must be reversed, or the X -input voltage must be
negative.
Z INPUT
±
10V FS
X INPUT
+0.1V TO
+10V
OPTIONAL
SUMMING
INPUT
±
10V FS
W = 10
+Y1
(Z
2
– Z
1
)
(X
1
– X
2
)
1
2
3
4
5
6
7
10
8
9
11
13
12
14
W
ER
VN
VP
DD
Z1
Z2
X1
X2
U1
U2
U0
Y1
Y2
AD734
NC
NC
0.1μF
0.1μF
+15V
–15V
L
L
Y
1
L
Figure 8. Standard (AD534) Divider Connection
T he numerator input, which is differential and can have either
polarity, is applied to pins Z1 and Z2. As with all dividers based
on feedback, the bandwidth is directly proportional to the
denominator, being 10 MHz for X = 10 V and reducing to
100 kHz for X = 100 mV. T his reduction in bandwidth, and the
increase in output noise (which is inversely proportional to the
denominator voltage) preclude operation much below a denomi-
nator of 100 mV. Division using direct control of the denominator
(Figure 10) does not have these shortcomings.
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