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參數(shù)資料
| 型號(hào)： | AD7339 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 5 V Integrated High Speed ADC/Quad DAC System(高速8位A/D轉(zhuǎn)換器/四路8位D/A轉(zhuǎn)換器) |
| 中文描述： | 5伏集成高速ADC /四路DAC系統(tǒng)（高速8位的A / D轉(zhuǎn)換器/四路8位的D / A轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 170K |
| 代理商： | AD7339 |
AD7339
–8–
REV. 0
Pin Number
Mnemonic
Function
11
DACPDB
Digital Input. The parallel DACs, VREFA and VREFB, can be powered down
using pin DACPDB. When DACPDB is low, both of the parallel DACs and the
VREFA/VREFB outputs are placed in a standby mode, drawing a minimal cur-
rent. The reference, which is available on the VREF pin, is not powered down.
Serial DACs
16
SDATA
Serial Input Data. Serial data is latched into the AD7339 registers on the rising
edge of SCLK. The digital data uses CMOS logic. Data is loaded into the latches
in 10-bit bursts (MSB first), the 2 MSBs of the word indicating the DAC to which
the digital word is being loaded while the 8 LSBs contain the digital word being
loaded into the DAC. The serial DACs use offset binary.
Serial Input Clock. Data is latched into the registers on the rising edge of SCLK,
which is nominally set to 256 kHz. SCLK is a gated clock—the clock should be active
only when data is being loaded into the latches. The clock should idle low between
conversions.
Latch Enable Input. LATCH is used to load the digital data from the latch into
the DAC and begin conversion. Both DACs are loaded with the digital data in
their respective latches. LATCH is pulsed high to load the DACs, the DACs being
loaded on the rising edge of LATCH.
Analog Output from Serial DAC0. The analog output from this DAC will have a
value of 0.2 V to AVDD – 0.247 V.
Feedback Analog Input. By connecting a resistor between SDAC0F and SDAC0S,
the gain of the DAC0 buffer can be altered and the magnitude of the analog out-
put adjusted accordingly.
Analog Output from Serial DAC1. The analog output from this DAC will have a
value of 0.2 V to AVDD – 0.247 V.
Feedback Analog Input. By connecting a resistor between SDAC1F and SDAC1S,
the gain of the DAC1 buffer can be altered and the magnitude of the analog out-
put adjusted accordingly.
Digital Input. The serial DACs are powered down using SDACPDB. When this
pin is tied low, the serial DACs are placed in standby mode.
14
SCLK
15
LATCH
38
SDAC0S
37
SDAC0F
40
SDAC1S
39
SDAC1F
13
SDACPDB
Reference
35
VREF
The onboard bandgap reference is available on the VREF pin. The reference has a
value of 2.5 V nominal. A bypass capacitor of 0.1
μ
F is required between VREF
and AGND. This output cannot be powered down.
A buffered version of the reference is available on VREFA/VREFB. The analog
outputs from the parallel DACs are biased about the reference voltage. DACA is
biased about VREFA while DACB is biased about VREFB. VREFA and VREFB
can be used with DACA and DACB to provide differential analog inputs to the
circuitry connected to the DACs. These outputs are powered down using DACPDB.
These outputs should be decoupled using a capacitance of 100 pF minimum.
44, 42
VREFA/VREFB
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