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參數(shù)資料
| 型號： | AD7339 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 5 V Integrated High Speed ADC/Quad DAC System(高速8位A/D轉(zhuǎn)換器/四路8位D/A轉(zhuǎn)換器) |
| 中文描述： | 5伏集成高速ADC /四路DAC系統(tǒng)（高速8位的A / D轉(zhuǎn)換器/四路8位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 170K |
| 代理商： | AD7339 |
–2–
REV. 0
AD7339–SPECIFICATIONS
1
Parameter
B Version
Units
Test Conditions/Comments
ADC
Resolution
Differential Nonlinearity
Integral Nonlinearity
Zero Input Offset Error
Signal Range
ADCCLK = 2.048 MHz
8
±
1
±
1
±
3
±
1
Bits
LSB max
LSB max
LSB
V max
8 Bits Monotonic
The input must be biased about 1.4 V. Therefore, ac
coupling with a 1 nF capacitor is needed if the bias
voltage does not equal 1.4 V. The input should be
driven with a maximum source impedance of 50
.
Full Power Input Bandwidth
Conversion Rate
Signal to (Noise + Distortion)
Effective No. of Bits (ENOB)
Intermodulation Distortion
Error Rate
Input Capacitance
Coding
1.024
2.048
42.7
6.8
48
4.7
×
10
11
5
Offset Binary
MHz
MSPS
dB min
Bits min
dB min
See Terminology
pF max
00H to FFH with 80H = 0 V
PARALLEL DACS
Resolution
Differential Nonlinearity
Integral Nonlinearity
Output Signal Range
V
SWING
V
BIAS
Update Rate
Bipolar Zero Offset Error
Gain Error
Output Harmonic Content in
Band 0 MHz to 1.152 MHz
Gain Matching Between DACs
Crosstalk
DACCLK = 2.304 MHz
8
±
1
±
1
V
BIAS
±
V
SWING
14/25
×
VREFA/B
VREFA/B
2.304
±
40
±
5
50
46
0.2
Bits
LSB max
LSB max
8 Bits Monotonic
V nom
V nom
MHz max
mV max
% typ
dB min
dB min
dB
VREFA/B means VREFA for DACA and VREFB for DACB.
Factory Trim. Does Not Include Gain Error
For a Full-Scale Digital Sine Wave in Band 0 kHz to 76.8 kHz
For a Full-Scale Digital Sine Wave in Band 0 kHz to 128 kHz
For Amplitudes Which Equal Full Scale –10 dB
1.8 k
Load Between DACA and VREFA, and Between
DACB and VREFB
A Channel has a full-scale output of frequency 128 kHz.
B Channel has a full-scale output of frequency 128 kHz.
A Channel has a full-scale output of frequency 128 kHz.
B Channel has a full-scale output of frequency 128 kHz.
Connected Between DACA/B and VREFA/B
To B Channel from A Channel
To A Channel from B Channel
To VREFB from A Channel
To VREFA from B Channel
Load Resistance
Load Capacitance
Full-Scale Settling Time
Coding
55
55
55
55
1.8
50
4
Offset Binary
dB min
dB min
dB min
dB min
k
min
pF max
μ
s typ
00H to FFH with 80H = Bias Voltage
SERIAL DACS
Resolution
Differential Nonlinearity
Integral Nonlinearity
Output Range
00H
FFH
Update Rate
Load Resistance
Load Capacitance
I
SINK
I
SOURCE
Full-Scale Settling Time
Coding
SCLK is a gated 256 kHz clock.
8
±
1
±
1.5
Bits
LSB
LSB
8 Bits Monotonic
With Respect to Full Scale
See Figure 1
0.2
AVDD – 0.247
SCLK/10
20
100
1
100
2.5
Straight Binary
V max
V min
kHz max
k
max
pF max
mA typ
μ
A typ
μ
s typ
When AVDD > 5.247 V, the analog output will equal 2 VREF.
(AVDD = DVDD = +5 V
6
10%, AGND = DGND = 0 V, T
A
= T
MIN
to T
MAX
, unless other-
wise noted)
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