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參數(shù)資料
| 型號： | AD7266BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/29頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 2MSPS 3CH 32LFCSP |
| 設(shè)計(jì)資源： | AD7266 SAR ADC in DC-Coupled Differential and Single-Ended Appls (CN0039) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 33.6mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 12 個(gè)單端，單極；6 個(gè)差分，單極；6 個(gè)偽差分，單極 |
| 其它名稱： | AD7266BCPZ-REEL7DKR |
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AD7266
Rev. B | Page 21 of 28
SCLK
DOUTA
DOUTB
INVALID DATA
VALID DATA
1
10
14
1
THE PART BEGINS
TO POWER UP.
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
tPOWER-UP2
CS
04603-033
Figure 38. Exiting Full Power-Down Mode
POWER-UP TIMES
As described in detail, the AD7266 has two power-down
modes, partial power-down and full power-down. This section
deals with the power-up time required when coming out of
either of these modes. It should be noted that the power-up
times, as explained in this section, apply with the recommended
capacitors in place on the DCAPA and DCAPB pins.
To power up from full power-down, approximately 1.5 ms
should be allowed from the falling edge of CS, shown as
tPOWER-UP2 in
. Powering up from partial power-down
requires much less time. The power-up time from partial
power-down is typically 1 μs; however, if using the internal
reference, then the AD7266 must be in partial power-down for
at least 67 μs in order for this power-up time to apply.
When power supplies are first applied to the AD7266, the ADC
may power up in either of the power-down modes or normal
mode. Because of this, it is best to allow a dummy cycle to
elapse to ensure the part is fully powered up before attempting a
valid conversion. Likewise, if it is intended to keep the part in
the partial power-down mode immediately after the supplies are
applied, then two dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10th SCLK falling
edge (see
); in the second cycle,
CS must be brought
high before the 10th SCLK edge but after the second SCLK
falling edge (see
). Alternatively, if it is intended to
place the part in full power-down mode when the supplies are
applied, then three dummy cycles must be initiated. The first
dummy cycle must hold
CS low until after the 10th SCLK falling
edge (see
); the second and third dummy cycles place
the part in full power-down (see
Once supplies are applied to the AD7266, enough time must be
allowed for any external reference to power up and charge the
various reference buffer decoupling capacitors to their final values.
POWER vs. THROUGHPUT RATE
The power consumption of the AD7266 varies with the
throughput rate. When using very slow throughput rates and as
fast an SCLK frequency as possible, the various power-down
options can be used to make significant power savings.
However, the AD7266 quiescent current is low enough that
even without using the power-down options, there is a
noticeable variation in power consumption with sampling rate.
This is true whether a fixed SCLK value is used or if it is scaled
power vs. the throughput rate when operating in normal mode
for a fixed maximum SCLK frequency and an SCLK frequency
that scales with the sampling rate with VDD = 3 V and VDD = 5 V,
respectively. In all cases, the internal reference was used.
04
60
3-
0
45
THROUGHPUT (kSPS)
1400
0
200
400
600
800
1000
1200
P
O
WER
(
m
W)
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
24MHz SCLK
VARIABLE SCLK
TA = 25°C
Figure 39. Power vs. Throughput in Normal Mode with VDD = 3 V
04
60
3-
04
6
THROUGHPUT (kSPS)
2000
0
200
400
600
800 1000 1200 1400 1600 1800
P
O
WE
R
(
m
W)
30
28
26
24
22
20
18
16
14
12
10
32MHz SCLK
VARIABLE SCLK
TA = 25°C
Figure 40. Power vs. Throughput in Normal Mode with VDD = 5 V
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