VDD C1 D VIN+ R1 C2
參數(shù)資料
型號： AD7265BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 7/29頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 3CHAN 1MSPS 32LFCSP
設計資源： AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048)
標準包裝： 1,500
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 21mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應商設備封裝： 32-LFCSP-VQ
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 12 個單端，單極；6 個差分，單極；6 個偽差分，單極
AD7265
Rev. A | Page 14 of 28
VDD
C1
D
VIN+
R1 C2
VDD
C1
D
VIN–
R1 C2
04674-
015
Figure 21 shows a graph of the THD vs. the analog input
frequency for various supplies while sampling at 1 MSPS. In this
case, the source impedance is 47 Ω.
04674-018
INPUT FREQUENCY (kHz)
600
0
200
100
400
300
500
THD
(dB)
–50
–60
–55
–65
–70
–75
–80
–85
–90
VDD = 3V
SINGLE-ENDED MODE
VDD = 5V
SINGLE-ENDED MODE
VDD = 3V
DIFFERENTIAL MODE
VDD = 5V
DIFFERENTIAL MODE
FSAMPLE = 1MSPS
VDD = 3V/5V
RANGE = 0 TO VREF
Figure 18. Equivalent Analog Input Circuit,
Conversion Phase—Switches Open, Track Phase—Switches Closed
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of THD that can be toler-
ated. The THD increases as the source impedance increases and
performance degrades.
Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages
Figure 19 shows a graph of the THD vs.
the analog input signal frequency for different source impedances
in single-ended mode, while
ANALOG INPUTS
Figure 20 shows the THD vs. the
analog input signal frequency for different source impedances
in differential mode.
The AD7265 has a total of 12 analog inputs. Each on-board
ADC has six analog inputs that can be configured as six single-
ended channels, three pseudo differential channels, or three
fully differential channels. These can be selected as described in
the
0
4674
-01
6
INPUT FREQUENCY (kHz)
600
0200
100
400
300
500
TH
D
(
dB
)
–50
–60
–55
–65
–70
–75
–80
–85
–90
FSAMPLE = 1MSPS
VDD = 3V
RANGE = 0V TO VREF
RSOURCE = 0
RSOURCE = 10
RSOURCE = 47
RSOURCE = 100
RSOURCE = 300
Single-Ended Mode
The AD7265 can have a total of 12 single-ended analog input
channels. In applications where the signal source has high
impedance, it is recommended to buffer the analog input before
applying it to the ADC. The analog input range can be pro-
grammed to be either 0 to V
or 0 to 2 × V
.
REF
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal to make it correctly formatted for the ADC. Figure 22
shows a typical connection diagram when operating the ADC
in single-ended mode.
Figure 19. THD vs. Analog Input Frequency for
Various Source Impedances, Single-Ended Mode
VIN
0V
+1.25V
–1.25V
DCAPA/DCAPB
VA1
VB6
R
3R
R
0V
+2.5V
0.47F
1ADDITIONAL PINS OMITTED FOR CLARITY.
04
67
4-
0
19
AD72651
04
674-
017
INPUT FREQUENCY (kHz)
600
0200
100
400
300
500
TH
D
(
dB
)
–60
–65
–70
–75
–80
–85
–90
FSAMPLE = 1MSPS
VDD = 3V
RANGE = 0V TO VREF
RSOURCE = 300
RSOURCE = 0
RSOURCE = 10
RSOURCE = 47
RSOURCE = 100
Figure 22. Single-Ended Mode Connection Diagram
Figure 20. THD vs. Analog Input Frequency for
Various Source Impedances, Differential Mode
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