- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10328 > AD7265BCPZ-REEL7 (Analog Devices Inc)IC ADC 12BIT 3CHAN 1MSPS 32LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD7265BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/29頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 3CHAN 1MSPS 32LFCSP |
| 設計資源： | AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048) |
| 標準包裝： | 1,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 21mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 12 個單端，單極；6 個差分，單極；6 個偽差分，單極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
AD7265
Rev. A | Page 23 of 28
MICROPROCESSOR INTERFACING
The connection diagram is shown in
The serial interface on the AD7265 allows the part to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7265 with some of the
more common microcontroller and DSP serial interface
protocols.
Figure 43. The ADSP-218x
has the TFS0 and RFS0 of the SPORT0 and the RFS1 of
SPORT1 tied together. TFS0 is set as an output, and both RFS0
and RFS1 are set as inputs. The DSP operates in alternate
framing mode, and the SPORT control register is set up as
described. The frame synchronization signal generated on the
TFS is tied to
AD7265 TO ADSP-218x
CS, and, as with all signal processing applications,
equidistant sampling is necessary. However, in this example, the
timer interrupt is used to control the sampling rate of the ADC
and, under certain conditions, equidistant sampling may not be
achieved.
The ADSP-218x family of DSPs interface directly to the
AD7265 without any glue logic required. The VDRIVE pin of the
AD7265 takes the same supply voltage as that of the ADSP-218x.
This allows the ADC to operate at a higher supply voltage than
its serial interface and, therefore, the ADSP-218x, if necessary.
This example shows both D
AD72651
SCLK
CS
ADSP-218x1
1ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK0
DR0
RFS0
TFS0
DOUTA
VDRIVE
VDD
DOUTB
DR1
RFS1
SCLK1
04
67
4-
0
36
A and D
OUT
B of the AD7265
connected to both serial ports of the ADSP-218x. The SPORT0
and SPORT1 control registers should be set up as shown in
Table 7. SPORT0 Control Register Setup
Setting
Description
TFSW = RFSW = 1
Alternate framing
INVRFS = INVTFS = 1
Active low frame signal
DTYPE = 00
Right justify data
SLEN = 1111
16-bit data-word (or may be set to
1101 for 14-bit data-word)
ISCLK = 1
Internal serial clock
TFSR = RFSR = 1
Frame every word
Figure 43. Interfacing the AD7265 to the ADSP-218x
IRFS = 0
ITFS = 1
The timer registers are loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS, and hence, the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given (AX0 = TX0), the state of the SCLK is checked. The
DSP waits until the SCLK has gone high, low, and high again
before transmission starts. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data may be transmitted or it
may wait until the next clock edge.
Table 8. SPORT1 Control Register Setup
Setting
Description
TFSW = RFSW = 1
Alternate framing
INVRFS = INVTFS = 1
Active low frame signal
DTYPE = 00
Right justify data
SLEN = 1111
16-bit data-word (or may be set to
1101 for 14-bit data-word)
ISCLK = 0
External serial clock
TFSR = RFSR = 1
Frame every word
IRFS = 0
ITFS = 1
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
then an SCLK of 2 MHz is obtained, and eight master clock
periods will elapse for every one SCLK period. If the timer
registers are loaded with the value 803, then 100.5 SCLKs will
occur between interrupts and, subsequently, between transmit
instructions. This situation yields sampling that is not equidistant,
as the transmit instruction is occurring on a SCLK edge. If the
number of SCLKs between interrupts is a whole integer figure
of N, then equidistant sampling will be implemented by the DSP.
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9283BRSZ-RL80 | IC ADC 8BIT 80MSPS 3V 20-SSOP |
| VE-24M-IU-S | CONVERTER MOD DC/DC 10V 200W |
| VI-2WF-MX-S | CONVERTER MOD DC/DC 72V 75W |
| MS27468E17F6B | CONN HSG RCPT 6POS JAMNUT SCKT |
| VI-B3W-IW-B1 | CONVERTER MOD DC/DC 5.5V 100W |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7265BSU | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC |
| AD7265BSUZ | 功能描述:IC ADC 12BIT 3CHAN 1MSPS 32TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7265BSUZ-REEL | 功能描述:IC ADC 12BIT 3CHAN 1MSPS 32TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:2,500 系列:- 位數(shù):16 采樣率（每秒）:15 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應商設備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數(shù)目和類型:16 個單端，雙極；8 個差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| AD7265BSUZ-REEL7 | 功能描述:IC ADC 12BIT 3CHAN 1MSPS 32TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD7266 | 制造商:Analog Devices 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。