參數(shù)資料
型號： AD7265BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 10/29頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 3CHAN 1MSPS 32LFCSP
設(shè)計(jì)資源： AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048)
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 21mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 12 個(gè)單端，單極；6 個(gè)差分，單極；6 個(gè)偽差分，單極
AD7265
Rev. A | Page 17 of 28
The channels used for simultaneous conversions are selected via
the multiplexer address input pins, A0 to A2. The logic states of
these pins also need to be established prior to the acquisition
time; however, they may change during the conversion time,
provided that the mode is not changed. If the mode is changed
from fully differential to pseudo-differential, for example, then
the acquisition time would start again from this point. The
selected input channels are decoded as shown in
ANALOG INPUT SELECTION
The analog inputs of the AD7265 can be configured as single-
ended or true differential via the SGL/DIFF logic pin, as shown
in Figure 31. If this pin is tied to a logic low, the analog input
channels to each on-chip ADC are set up as three true differen-
tial pairs. If this pin is at logic high, the analog input channels to
each on-chip ADC are set up as six single-ended analog inputs.
The required logic level on this pin needs to be established prior
to the acquisition time and remain unchanged during the con-
version time until the track-and-hold has returned to track. The
track-and-hold returns to track on the 13
The analog input range of the AD7265 can be selected as 0 V to
V
or 0 V to 2 × V
REF
via the RANGE pin. This selection is
made in a similar fashion to that of the SGL/DIFF pin by setting
the logic state of the RANGE pin a time t
th rising edge of SCLK
after the CS falling edge (see Figure 41). If the level on this pin
is changed, it is recognized by the AD7265; therefore, it is
necessary to keep the same logic level during acquisition and
conversion to avoid corrupting the conversion in progress.
acq
prior to the falling
edge of CS. Subsequent to this, the logic level on this pin can be
altered after the third falling edge of SCLK. If this pin is tied to a
logic low, the analog input range selected is 0 V to VREF. If this
pin is tied to a logic high, the analog input range selected is 0 V
to 2 × V
DIFF
For example, in Figure 31, the SGL/
pin is set at logic high
for the duration of both the acquisition and conversion times
so the analog inputs are configured as single ended for that
conversion (Sampling Point A). The logic level of the SGL/
REF
.
OUTPUT CODING
DIFF
changed to low after the track-and-hold returned to track and
prior to the required acquisition time for the next sampling
instant at Point B; therefore, the analog inputs are configured as
differential for that conversion.
The AD7265 output coding is set to either twos complement or
straight binary, depending on which analog input configuration
is selected for a conversion. Table 5 shows which output coding
scheme is used for each possible analog input configuration.
Table 5. AD7265 Output Coding
SCLK
CS
114
14
1
A
SGL/DIFF
B
tACQ
04674-026
Figure 31. Selecting Differential or Single-Ended Configuration
SGL/DIFF
Range
Output Coding
DIFF
0 V to V
Twos complement
REF
DIFF
0 V to 2 × VREF
Twos complement
SGL
0 V to VREF
Straight binary
SGL
0 V to 2 × VREF
Twos complement
PSEUDO DIFF
0 V to VREF
Straight binary
PSEUDO DIFF
0 V to 2 × V
Twos complement
REF
Table 6. Analog Input Type and Channel Selection
ADC A
ADC B
SGL/DIFF
V
A2
A1
A0
VIN+
IN
IN+
IN
Comment
1
0
V
AGND
V
AGND
Single ended
A1
B1
1
0
1
V
AGND
V
AGND
A2
B2
Single ended
1
0
1
0
V
AGND
V
AGND
A3
B3
Single ended
1
0
1
V
AGND
V
AGND
A4
B4
Single ended
1
0
V
AGND
V
AGND
A5
B5
Single ended
1
0
1
V
AGND
V
AGND
A6
B6
Single ended
0
V
A1
A2
B1
VB2
Fully differential
0
1
V
A1
A2
B1
B2
Pseudo differential
0
1
0
V
A3
A4
B3
VB4
Fully differential
0
1
V
A3
A4
B3
B4
Pseudo differential
0
1
0
V
A5
A6
B5
VB6
Fully differential
0
1
0
1
V
Pseudo differential
A5
A6
B5
B6
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