參數(shù)資料
型號(hào)： AD7226KP
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： LC2MOS Quad 8-Bit D/A Converter
中文描述： PARALLEL, 8 BITS INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, PQCC20
封裝： PLASTIC, MO-047AA, LCC-20
文件頁(yè)數(shù)： 8/12頁(yè)
文件大?。?/td> 247K
代理商： AD7226KP
AD7226
REV. A
–8–
Unipolar Output Operation
T his is the basic mode of operation for each channel of the
AD7226, with the output voltage having the same positive
polarity as +V
REF
. T he AD7226 can be operated single supply
(V
SS
= AGND) or with positive/negative supplies (see op-amp
section which outlines the advantages of having negative V
SS
).
T he code table for unipolar output operation is shown in T able
II. Note that the voltage at V
REF
must never be negative with re-
spect to DGND in order to prevent parasitic transistor turn-on.
Connections for the unipolar output operation are shown in Fig-
ure 12.
Figure 12. AD7226 Unipolar Output Circuit
T able II. Unipolar Code T able
DAC Latch Contents
MSB
LSB
Analog Output
1 1 1 1
1 1 1 1
+
V
REF
255
256
1 0 0 0
0 0 0 1
+
V
REF
129
256
V
REF
1 0 0 0
0 0 0 0
+
V
REF
128
256
2
0 1 1 1
1 1 1 1
+
V
REF
127
256
0 0 0 0
0 0 0 1
+
V
REF
1
256
0 0 0 0
0 0 0 0
0 V
Note
: 1
LSB
=
V
REF
(
)
2
8
(
)
=
V
REF
1
256
Bipolar Output Operation
Each of the DACs of the AD7226 can be individually config-
ured to provide bipolar output operation. T his is possible using
one external amplifier and two resistors per channel. Figure 13
shows a circuit used to implement offset binary coding (bipolar
operation) with DAC A of the AD7226. In this case
V
OUT
=
1
+
R
2
R
1
D
A
V
REF
(
)
±
R
2
R
1
V
REF
(
)
With
R
1 =
R
2
V
OUT
= (2
D
A
– 1)
V
REF
where
D
A
is a fractional representation of the digital word in
latch A.
Mismatch between R1 and R2 causes gain and offset errors and
therefore these resistors must match and track over temperature.
Once again the AD7226 can be operated in single supply or
from positive/negative supplies. T able III shows the digital code
versus output voltage relationship for the circuit of Figure 13
with R1 = R2.
Figure 13. AD7226 Bipolar Output Circuit
T able III. Bipolar (Offset Binary) Code T able
DAC Latch Contents
MSB
LSB
Analog Output
1 1 1 1
1 1 1 1
+
V
REF
127
128
1 0 0 0
0 0 0 1
+
V
REF
1
128
1 0 0 0
0 0 0 0
0 V
0 1 1 1
1 1 1 1
±
V
REF
1
128
0 0 0 0
0 0 0 1
±
V
REF
127
128
0 0 0 0
0 0 0 0
±
V
REF
128
128
±
V
REF
AGND BIAS
T he AD7226 AGND pin can be biased above system GND
(AD7226 DGND) to provide an offset “zero” analog output
voltage level. Figure 14 shows a circuit configuration to achieve
this for channel A of the AD7226. T he output voltage, V
OUT A
,
can be expressed as:
V
OUTA
=
V
BIAS
+
D
A
(
V
IN
)
where
D
A
is a fractional representation of the digital input
word (0
≤
D
≤
255/256).
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