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參數(shù)資料
| 型號： | AD7226KP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Quad 8-Bit D/A Converter |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, PQCC20 |
| 封裝： | PLASTIC, MO-047AA, LCC-20 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 247K |
| 代理商： | AD7226KP |
AD7226
REV. A
–5–
CIRCUIT INFORMAT ION
D/A SE CT ION
T he AD7226 contains four, identical, 8-bit, voltage mode
digital-to-analog converters. T he output voltages from the con-
verters have the same polarity as the reference voltage allowing
single supply operation. A novel DAC switch pair arrangement
on the AD7226 allows a reference voltage range from +2 V to
+12.5 V.
Each DAC consists of a highly stable, thin-film, R-2R ladder
and eight high speed NMOS, single-pole, double-throw
switches. T he simplified circuit diagram for one channel is
shown in Figure 1. Note that V
REF
(Pin 4) and AGND (Pin 5)
are common to all four DACs.
Figure 1. D/A Simplified Circuit Diagram
T he input impedance at the V
REF
pin of the AD7226 is the par-
allel combination of the four individual DAC reference input
impedances. It is code dependent and can vary from 2 k
to in-
finity. T he lowest input impedance (i.e., 2 k
) occurs when all
four DACs are loaded with the digital code 01010101. T here-
fore, it is important that the reference presents a low output im-
pedance under changing load conditions. T he nodal capacitance
at the reference terminals is also code dependent and typically
varies from 100 pF to 250 pF.
Each V
OUT
pin can be considered as a digitally programmable
voltage source with an output voltage of:
V
OUT X
= D
X
V
REF
where D
X
is fractional representation of the digital input code
and can vary from 0 to 255/256.
T he source impedance is the output resistance of the buffer
amplifier.
OP AMP SE CT ION
Each voltage-mode D/A converter output is buffered by a unity
gain, noninverting CMOS amplifier. T his buffer amplifier is
capable of developing +10 V across a 2 k
load and can drive
capacitive loads of 3300 pF. T he output stage of this amplifier
consists of a bipolar transistor from the V
DD
line and a current
load to the V
SS
, the negative supply for the output amplifiers.
T his output stage is shown in Figure 2.
T he NPN transistor supplies the required output current drive
(up to 5 mA). T he current load consists of NMOS transistors
which normally act as a constant current sink of 400
μ
A to V
SS
,
giving each output a current sink capability of approximately
400
μ
A if required.
T he AD7226 can be operated single or dual supply resulting
in different performance in some parameters from the output
amplifiers.
In single supply operation (V
SS
= 0 V = AGND), with the out-
put approaching AGND (i.e., digital code approaching all 0s)
Figure 2. Amplifier Output Stage
the current load ceases to act as a current sink and begins to act
as a resistive load of approximately 2 k
to AGND. T his occurs
as the NMOS transistors come out of saturation. T his means
that, in single supply operation, the sink capability of the ampli-
fiers is reduced when the output voltage is at or near AGND. A
typical plot of the variation of current sink capability with out-
put voltage is shown in Figure 3.
Figure 3. Variation of I
SINK
with V
OUT
If the full sink capability is required with output voltages at or
near AGND (=0 V), then V
SS
can be brought below 0 V by 5 V
and thereby maintain the 400
μ
A current sink as indicated in
Figure 3. Biasing V
SS
below 0 V also gives additional headroom
in the output amplifier which allows for better zero code error
performance on each output. Also improved is the slew-rate
and negative-going settling-time of the amplifiers (discussed
later).
Each amplifier offset is laser trimmed during manufacture to
eliminate any requirement for offset nulling.
DIGIT AL SE CT ION
T he digital inputs of the AD7226 are both T T L and CMOS
(5 V) compatible from V
DD
= +11.4 V to +16.5 V. All logic in-
puts are static protected MOS gates with typical input currents
of less than 1 nA. Internal input protection is achieved by an
on-chip distributed diode from DGND to each MOS gate. T o
minimize power supply currents, it is recommended that the
digital input voltages be driven as close to the supply rails (V
DD
and DGND) as practically possible.
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