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參數(shù)資料
| 型號(hào)： | AD7225UQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Quad 8-Bit DAC with Separate Reference Inputs |
| 中文描述： | QUAD, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, CDIP24 |
| 封裝： | CERDIP-24 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 339K |
| 代理商： | AD7225UQ |
REV. B
–2–
AD7225–SPECIFICATIONS
(V
DD
= 11.4 V to 16.5 V, V
SS
= –5 V
6
10%; AGND = DGND = OV; V
REF
= +2 V to (V
DD
– 4 V)
1
unless otherwse noted.
All specifications T
MN
to T
MAX
unless otherwse noted.)
DUAL SUPPLY
K, B
Versions
2
L, C
Versions
2
Parameter
T Version
U Version
Units
Conditions/Comments
ST AT IC PERFORMANCE
Resolution
T otal Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Full-Scale T emp. Coeff.
Zero Code Error @ 25
°
C
T
to T
Zero Code Error T emp Coeff.
8
±
2
±
1
±
1
±
1
±
5
±
25
±
30
±
30
8
±
1
±
1/2
±
1
±
1/2
±
5
±
15
±
20
±
30
8
±
2
±
1
±
1
±
1
±
5
±
25
±
30
±
30
8
±
1
±
1/2
±
1
±
1/2
±
5
±
15
±
20
±
30
Bits
LSB max
LSB max
LSB max
LSB max
ppm/
°
C typ
mV max
mV max
μ
V/
°
C typ
V
DD
= +15 V
±
5%, V
REF
= +10 V
Guaranteed Monotonic
V
DD
= 14 V to 16.5 V, V
REF
= +10 V
REFERENCE INPUT
Voltage Range
Input Resistance
Input Capacitance
3
Channel-to-Channel Isolation
3
AC Feedthrough
2 to (V
DD
– 4)
11
100
60
–70
2 to (V
DD
– 4)
11
100
60
–70
2 to (V
DD
– 4)
11
100
60
–70
2 to (V
DD
– 4)
11
100
60
–70
V min to V max
k
min
pF max
dB min
dB max
Occurs when each DAC is loaded with all 1s.
V
REF
= 10 V p-p Sine Wave @ 10 kHz
V
REF
= 10 V p-p Sine Wave @ 10 kHz
DIGIT AL INPUT S
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Leakage Current
Input Capacitance
Input Coding
2.4
0.8
±
1
8
Binary
2.4
0.8
±
1
8
Binary
2.4
0.8
±
1
8
Binary
2.4
0.8
±
1
8
Binary
V min
V max
μ
A max
pF max
V
IN
= 0 V or V
DD
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
3
Voltage Output Settling T ime
3
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
Digital Crosstalk
Minimum Load Resistance
2.5
2.5
2.5
2.5
V/
μ
s min
5
5
50
50
2
5
5
50
50
2
5
5
50
50
2
5
5
50
50
2
μ
s max
μ
s max
nV secs typ
nV secs typ
k
min
V
REF
= +10 V; Settling T ime to
±
1/2 LSB
V
= +10 V; Settling T ime to
±
1/2 LSB
Code transition all 0s to all 1s.
Code transition all 0s to all 1s.
V
OUT
= +10 V
POWER SUPPLIES
V
DD
Range
I
DD
I
SS
11.4/16.5
10
9
11.4/16.5
10
9
11.4/16.5
12
10
11.4/16.5
12
10
V min to V max For Specified Performance
mA max
Outputs Unloaded; V
IN
= V
INL
or V
INH
mA max
Outputs Unloaded; V
IN
= V
INL
or V
INH
SWIT CHING CHARACT ERIST ICS
3, 4
t
1
@ 25
°
C
T
MIN
to T
MAX
t
2
@ 25
°
C
T
MIN
to T
MAX
t
3
@ 25
°
C
T
MIN
to T
MAX
t
4
@ 25
°
C
T
MIN
to T
MAX
t
5
@ 25
°
C
T
MIN
to T
MAX
t
6
@ 25
°
C
T
MIN
to T
MAX
95
120
95
120
95
150
95
150
ns min
ns min
Write Pulse Width
0
0
0
0
0
0
0
0
ns min
ns min
Address to Write Setup T ime
0
0
0
0
0
0
0
0
ns min
ns min
Address to Write Hold T ime
70
90
70
90
70
90
70
90
ns min
ns min
Data Valid to Write Setup T ime
10
10
10
10
10
10
10
10
ns min
ns min
Data Valid to Write Hold T ime
95
120
95
120
95
150
95
150
ns min
ns min
Load DAC Pulse Width
NOT ES
1
Maximum possible reference voltage.
2
T emperature ranges are as follows:
K , L Versions: –40
°
C to +85
°
C
B, C Versions: –40
°
C to +85
°
C
T , U Versions: –55
°
C to +125
°
C
3
Sample T ested at 25
°
C to ensure compliance.
4
Switching characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
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