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參數(shù)資料
| 型號(hào)： | AD7225LR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Quad 8-Bit DAC with Separate Reference Inputs |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO24 |
| 封裝： | ROHS COMPLIANT, MS-013AD, SOIC-24 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 339K |
| 代理商： | AD7225LR |
AD7225
REV. B
–8–
SPE CIFICAT ION RANGE S
For the AD7225 to operate to rated specifications, its input ref-
erence voltage must be at least 4 V below the V
DD
power supply
voltage. T his voltage differential is the overhead voltage re-
quired by the output amplifiers.
T he AD7225 is specified to operate over a V
DD
range from
+12 V
±
5% to +15 V
±
10% (i.e., from +11.4 V to +16.5 V)
with a V
SS
of –5 V
±
10%. Operation is also specified for a single
+15 V
±
5% V
DD
supply. Applying a V
SS
of –5 V results in im-
proved zero code error, improved output sink capability with
outputs near AGND and improved negative going settling time.
Performance is specified over a wide range of reference voltages
from 2 V to (V
DD
– 4 V) with dual supplies. T his allows a range
of standard reference generators to be used such as the AD580,
a +2.5 V bandgap reference and the AD584, a precision +10 V
reference. Note that an output voltage range of 0 V to +10 V re-
quires a nominal +15 V
±
5% power supply voltage.
UNIPOLAR OUT PUT OPE RAT ION
T his is the basic mode of operation for each channel of the
AD7225, with the output voltage having the same positive
polarity as V
REF
. T he AD7225 can be operated single supply
(V
SS
= AGND) or with positive/negative supplies (see op-amp
section which outlines the advantages of having negative V
SS
).
Connections for the unipolar output operation are shown in Fig-
ure 13. T he voltage at any of the reference inputs must never be
negative with respect to DGND. Failure to observe this precau-
tion may cause parasitic transistor action and possible device de-
struction. T he code table for unipolar output operation is shown
in T able III.
Figure 13. Unipolar Output Circuit
T able III. Unipolar Code T able
DAC Latch Contents
MSB
LSB
Analog Output
1 1 1 1
1 1 1 1
+
V
REF
255
256
1 0 0 0
0 0 0 1
+
V
REF
129
256
1 0 0 0
0 0 0 0
+
V
REF
128
256
= +
V
REF
2
0 1 1 1
1 1 1 1
+
V
REF
127
256
0 0 0 0
0 0 0 1
+
V
REF
1
256
0 0 0 0
0 0 0 0
0 V
Note
: 1
LSB
=
V
REF
(
)
2
8
(
)
=
V
REF
1
256
BIPOLAR OUT PUT OPE RAT ION
Each of the DACs of the AD7225 can be individually config-
ured to provide bipolar output operation. T his is possible using
one external amplifier and two resistors per channel. Figure 14
shows a circuit used to implement offset binary coding (bipolar
operation) with DAC A of the AD7225. In this case
V
OUT
=
1
+
R
2
R
1
D
A
V
REF
(
)
±
R
2
R
1
V
REF
(
)
With
R
1 =
R
2
V
OUT
= (2
D
A
– 1)
V
REF
where
D
A
is a fractional representation of the digital word in
latch A. (0
≤
D
A
≤
255/256)
Mismatch between R1 and R2 causes gain and offset errors and,
therefore, these resistors must match and track over tempera-
ture. Once again the AD7225 can be operated in single supply
or from positive/negative supplies. T able IV shows the digital
code versus output voltage relationship for the circuit of Figure
14 with R1 = R2.
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